SHARC not SPARC

On 8/04/2018 2:53 PM, Alan Beard wrote:
Hi,
I used to be a full on SPARC guy but my Sun Ultra 5 is a bit old now (1999).

Should I try on my Banana Pi M1 and SATA SSD, the FreeDV app?

Dual Core armv7hl @ 1GHz with 1Gb ram and, a real SATA disk interface.
This allows real swap space and huge disk throughput.

At about $70 AU is a bargain for a FULL linux box.
(Fedora 25 or later is my choice)
(and an SSD or hard disk of course)

I read the specs on the ESP32, DMA only points at the internal memory
so a High Speed disk interface is a problem.

BTW: I decided to upgrade my Banana Pi with a Banana Pi M2 Berry but
the linux software support is not there yet. No GUI on the HDMI video.
Debian boots but I can't get XRDP to work. Also Debian uses the 3.10.xx
kernel which is old now, as does other Debian based distributions for ARM.
WHAT A PAIN.

Fedora 25 on the original Banana Pi works, a dream.


73 - isn't that an old electron tube? (HV triode)

Alan VK2ZIW


On Sun, 8 Apr 2018 10:55:59 +1000, glen english wrote
I generally assume for estimations, FPU ops = INT ops per clock, and
if you are careful you can do simultaneous INt/FPU ops...

Just watch out for non aligned floating point accesses. bang... not
lots of __aligned__ used.

I used to be a full-on SHARC guy. but I wonder where that market is
now with M7 and M4F around , and NEON which if you know what you are
doing can run rings around a SHARC.

Just diehards i think. The simple thigns with SHARC have disappeared
with cache involvement.

On 8/04/2018 10:51 AM, Dana Myers wrote:
On 4/7/2018 5:22 PM, Bruce Perens wrote:
It could also be the use of memory barrier instructions. I'd like to
benchmark Codec2 rather than a simple floating point loop with
volatile variables. But if we are to believe the times on the screen
of the esp32 in the video, he was getting acceptable performance.
 From what I've seen, the Cortex-M FPUs basically give single-precision
FP add/sub/mul in the same number of clocks as integer operations.

With a proper program store cache, Cortex-M4F is quite the rocket,
really.

Now I want to hunt down the appropriate Tensilica reference for the core
in the ESP32; it occurs to me the two cores may be sharing one FPU,
though I don't immediately see how the simple test would incur context
switching frequently.

73,
Dana  K6JQ


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Alan

Evil flourishes when good men do nothing.
Consider the Christmas child.
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Alan Beard               Unix Support Technician from 1984 to today
70 Wedmore Rd.           Sun Solaris, AIX, HP/UX, Linux, SCO, MIPS
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0414 353013 (mobile)     After uni, electronics tech


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