This patch adds the RISC-V Zvdota and Zvbdota extension families[1] and their implied dependencies to the RISC-V target. The Zvdota family covers non-batched dot-product instructions while Zvbdota adds batched variants with an EMUL=8 VS2 register group and a scaled ci immediate. The integer, BF16 and FP8 forms use the vtype altfmt field to select the VS1 interpretation where required.
[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zvfwdota16bf and Zvfwbdota16bf to the BF16 ELEN flag table. * config/riscv/riscv-ext.def: Add Zvdota and Zvbdota extensions. * config/riscv/riscv-ext.opt: Ditto. * doc/riscv-ext.texi: Ditto. --- gcc/common/config/riscv/riscv-common.cc | 4 + gcc/config/riscv/riscv-ext.def | 119 ++++++++++++++++++++++++ gcc/config/riscv/riscv-ext.opt | 21 +++++ gcc/doc/riscv-ext.texi | 36 +++++++ 4 files changed, 180 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index ed5d6839e92..850453d7f7e 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1482,6 +1482,10 @@ static const riscv_extra_ext_flag_table_t riscv_extra_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zve64d", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64), RISCV_EXT_FLAG_ENTRY ("zvfbfmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), RISCV_EXT_FLAG_ENTRY ("zvfbfwma", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_BF_16), + RISCV_EXT_FLAG_ENTRY ("zvfwdota16bf", x_riscv_vector_elen_flags, + MASK_VECTOR_ELEN_BF_16), + RISCV_EXT_FLAG_ENTRY ("zvfwbdota16bf", x_riscv_vector_elen_flags, + MASK_VECTOR_ELEN_BF_16), RISCV_EXT_FLAG_ENTRY ("zvfhmin", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), RISCV_EXT_FLAG_ENTRY ("zvfh", x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16), RISCV_EXT_FLAG_ENTRY ("zvfofp8min", x_riscv_vector_elen_flags, diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def index b9ef0c5ea05..b2dee1e4141 100644 --- a/gcc/config/riscv/riscv-ext.def +++ b/gcc/config/riscv/riscv-ext.def @@ -1156,6 +1156,19 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ 62, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ zvfbdota32f, + /* UPPERCASE_NAME */ ZVFBDOTA32F, + /* FULL_NAME */ "Vector FP32 batched dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ zvfbfmin, /* UPPERCASE_NAME */ ZVFBFMIN, @@ -1182,6 +1195,58 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ zvfqwbdota8f, + /* UPPERCASE_NAME */ ZVFQWBDOTA8F, + /* FULL_NAME */ "Vector quad-widening FP8 batched dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfqwdota8f, + /* UPPERCASE_NAME */ ZVFQWDOTA8F, + /* FULL_NAME */ "Vector quad-widening FP8 dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfwbdota16bf, + /* UPPERCASE_NAME */ ZVFWBDOTA16BF, + /* FULL_NAME */ "Vector widening BF16 batched dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvfwdota16bf, + /* UPPERCASE_NAME */ ZVFWDOTA16BF, + /* FULL_NAME */ "Vector widening BF16 dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32f"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvf, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ zvfbfwma, /* UPPERCASE_NAME */ ZVFBFWMA, @@ -1403,6 +1468,60 @@ DEFINE_RISCV_EXT( /* BITMASK_BIT_POSITION*/ 59, /* EXTRA_EXTENSION_FLAGS */ 0) +DEFINE_RISCV_EXT( + /* NAME */ zvqwbdota8i, + /* UPPERCASE_NAME */ ZVQWBDOTA8I, + /* FULL_NAME */ "Vector quad-widening 8-bit integer batched " + "dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvq, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvqwbdota16i, + /* UPPERCASE_NAME */ ZVQWBDOTA16I, + /* FULL_NAME */ "Vector quad-widening 16-bit integer batched " + "dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvq, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvqwdota8i, + /* UPPERCASE_NAME */ ZVQWDOTA8I, + /* FULL_NAME */ "Vector quad-widening 8-bit integer dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve32x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvq, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + +DEFINE_RISCV_EXT( + /* NAME */ zvqwdota16i, + /* UPPERCASE_NAME */ ZVQWDOTA16I, + /* FULL_NAME */ "Vector quad-widening 16-bit integer dot-product extension", + /* DESC */ "", + /* URL */ , + /* DEP_EXTS */ ({"zve64x"}), + /* SUPPORTED_VERSIONS */ ({{1, 0}}), + /* FLAG_GROUP */ zvq, + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, + /* EXTRA_EXTENSION_FLAGS */ 0) + DEFINE_RISCV_EXT( /* NAME */ zvl1024b, /* UPPERCASE_NAME */ ZVL1024B, diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt index 802c9eb4170..cc71a5f3fe0 100644 --- a/gcc/config/riscv/riscv-ext.opt +++ b/gcc/config/riscv/riscv-ext.opt @@ -106,6 +106,9 @@ int riscv_zvk_subext TargetVariable int riscv_zvl_subext +TargetVariable +int riscv_zvq_subext + Mask(RVE) Var(riscv_base_subext) Mask(RVI) Var(riscv_base_subext) @@ -264,10 +267,20 @@ Mask(ZVE64F) Var(riscv_zve_subext) Mask(ZVE64X) Var(riscv_zve_subext) +Mask(ZVFBDOTA32F) Var(riscv_zvf_subext) + Mask(ZVFBFMIN) Var(riscv_zvf_subext) Mask(ZVFOFP8MIN) Var(riscv_zvf_subext) +Mask(ZVFQWBDOTA8F) Var(riscv_zvf_subext) + +Mask(ZVFQWDOTA8F) Var(riscv_zvf_subext) + +Mask(ZVFWBDOTA16BF) Var(riscv_zvf_subext) + +Mask(ZVFWDOTA16BF) Var(riscv_zvf_subext) + Mask(ZVFBFWMA) Var(riscv_zvf_subext) Mask(ZVFH) Var(riscv_zvf_subext) @@ -302,6 +315,14 @@ Mask(ZVKSH) Var(riscv_zvk_subext) Mask(ZVKT) Var(riscv_zvk_subext) +Mask(ZVQWBDOTA8I) Var(riscv_zvq_subext) + +Mask(ZVQWBDOTA16I) Var(riscv_zvq_subext) + +Mask(ZVQWDOTA8I) Var(riscv_zvq_subext) + +Mask(ZVQWDOTA16I) Var(riscv_zvq_subext) + Mask(ZVL1024B) Var(riscv_zvl_subext) Mask(ZVL128B) Var(riscv_zvl_subext) diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi index 728cde737a7..47b44a7e940 100644 --- a/gcc/doc/riscv-ext.texi +++ b/gcc/doc/riscv-ext.texi @@ -334,6 +334,10 @@ @tab 1.0 @tab Vector extensions for embedded processors +@item @samp{zvfbdota32f} +@tab 1.0 +@tab Vector FP32 batched dot-product extension + @item @samp{zvfbfmin} @tab 1.0 @tab Vector BF16 converts extension @@ -342,6 +346,22 @@ @tab 0.2 @tab Vector FP8 minimum extension +@item @samp{zvfqwbdota8f} +@tab 1.0 +@tab Vector quad-widening FP8 batched dot-product extension + +@item @samp{zvfqwdota8f} +@tab 1.0 +@tab Vector quad-widening FP8 dot-product extension + +@item @samp{zvfwbdota16bf} +@tab 1.0 +@tab Vector widening BF16 batched dot-product extension + +@item @samp{zvfwdota16bf} +@tab 1.0 +@tab Vector widening BF16 dot-product extension + @item @samp{zvfbfwma} @tab 1.0 @tab Vector BF16 widening multiply/add extension @@ -410,6 +430,22 @@ @tab 1.0 @tab Vector data independent execution latency extension +@item @samp{zvqwbdota8i} +@tab 1.0 +@tab Vector quad-widening 8-bit integer batched dot-product extension + +@item @samp{zvqwbdota16i} +@tab 1.0 +@tab Vector quad-widening 16-bit integer batched dot-product extension + +@item @samp{zvqwdota8i} +@tab 1.0 +@tab Vector quad-widening 8-bit integer dot-product extension + +@item @samp{zvqwdota16i} +@tab 1.0 +@tab Vector quad-widening 16-bit integer dot-product extension + @item @samp{zvl1024b} @tab 1.0 @tab Minimum vector length standard extensions -- 2.43.0
