On 6/11/2026 1:54 AM, Jiawei wrote: > This patch adds the RISC-V Zvdota and Zvbdota extension families[1] and > their implied dependencies to the RISC-V target. The Zvdota family covers > non-batched dot-product instructions while Zvbdota adds batched > variants with an EMUL=8 VS2 register group and a scaled ci immediate. > The integer, BF16 and FP8 forms use the vtype altfmt field to select the > VS1 interpretation where required. > > [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add Zvfwdota16bf and > Zvfwbdota16bf to the BF16 ELEN flag table. > * config/riscv/riscv-ext.def: Add Zvdota and Zvbdota extensions. > * config/riscv/riscv-ext.opt: Ditto. > * doc/riscv-ext.texi: Ditto. OK, assuming the assembler support is already in place.
Jeff
