From: Pan Li <[email protected]>
Like v[sz]ext.vf8, allow the rvv register overlap
for vfwcvt.f.x[u].v.
gcc/ChangeLog:
* config/riscv/vector.md: Leverage Wvr constraint.
Signed-off-by: Pan Li <[email protected]>
---
gcc/config/riscv/vector.md | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 7566db97d14..44dfe003f31 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7867,19 +7867,19 @@ (define_insn "@pred_widen_<fix_cvt><mode>"
(set_attr "mode" "<VNCONVERT>")])
(define_insn "@pred_widen_<float_cvt><mode>"
- [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vd, vd")
(if_then_else:V_VLSF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rvl, rvl")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm")
+ (match_operand 4 "vector_length_operand" "rvl,rvl,rvl,rvl")
+ (match_operand 5 "const_int_operand" " i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_float:V_VLSF
- (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
- (match_operand:V_VLSF 2 "vector_merge_operand" " vu,
0")))]
+ (match_operand:<VNCONVERT> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
0")))]
"TARGET_VECTOR"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
--
2.43.0
