From: Pan Li <[email protected]>
Add test cases for vfwcvt.f.x.v register group overlap, please
note it is not overlap as much as possible.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c: New
test.
* gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c: New
test.
Signed-off-by: Pan Li <[email protected]>
---
.../autovec/group_overlap/vfwcvt_f_x-i16-m1.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i16-m2.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i16-m4.c | 17 ++++++++++
.../group_overlap/vfwcvt_f_x-i16-mf2.c | 31 +++++++++++++++++++
.../group_overlap/vfwcvt_f_x-i16-mf4.c | 31 +++++++++++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i32-m1.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i32-m2.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i32-m4.c | 17 ++++++++++
.../group_overlap/vfwcvt_f_x-i32-mf2.c | 31 +++++++++++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-m1.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-m2.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-m4.c | 17 ++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-mf2.c | 31 +++++++++++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-mf4.c | 31 +++++++++++++++++++
.../autovec/group_overlap/vfwcvt_f_x-i8-mf8.c | 31 +++++++++++++++++++
15 files changed, 339 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c
new file mode 100644
index 00000000000..28b5561f651
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vint16m1_t,
+ vfloat32m2_t,
+ __riscv_vle16_v_i16m1,
+ __riscv_vfwcvt_f_x_v_f32m2,
+ __riscv_vse32_v_f32m2,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c
new file mode 100644
index 00000000000..ae310a1c81a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m2,
+ vint16m2_t,
+ vfloat32m4_t,
+ __riscv_vle16_v_i16m2,
+ __riscv_vfwcvt_f_x_v_f32m4,
+ __riscv_vse32_v_f32m4,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c
new file mode 100644
index 00000000000..e41f7f0a275
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m4,
+ vint16m4_t,
+ vfloat32m8_t,
+ __riscv_vle16_v_i16m4,
+ __riscv_vfwcvt_f_x_v_f32m8,
+ __riscv_vse32_v_f32m8,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c
new file mode 100644
index 00000000000..fd5053c75d7
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vint16mf2_t,
+ vfloat32m1_t,
+ __riscv_vle16_v_i16mf2,
+ __riscv_vfwcvt_f_x_v_f32m1,
+ __riscv_vse32_v_f32m1,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c
new file mode 100644
index 00000000000..8b9f7051190
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i16-mf4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e16m1,
+ vint16mf4_t,
+ vfloat32mf2_t,
+ __riscv_vle16_v_i16mf4,
+ __riscv_vfwcvt_f_x_v_f32mf2,
+ __riscv_vse32_v_f32mf2,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c
new file mode 100644
index 00000000000..6bbcdb5e5b9
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vint32m1_t,
+ vfloat64m2_t,
+ __riscv_vle32_v_i32m1,
+ __riscv_vfwcvt_f_x_v_f64m2,
+ __riscv_vse64_v_f64m2,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c
new file mode 100644
index 00000000000..c4449da6066
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m2,
+ vint32m2_t,
+ vfloat64m4_t,
+ __riscv_vle32_v_i32m2,
+ __riscv_vfwcvt_f_x_v_f64m4,
+ __riscv_vse64_v_f64m4,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c
new file mode 100644
index 00000000000..8ce0c122c14
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m4,
+ vint32m4_t,
+ vfloat64m8_t,
+ __riscv_vle32_v_i32m4,
+ __riscv_vfwcvt_f_x_v_f64m8,
+ __riscv_vse64_v_f64m8,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c
new file mode 100644
index 00000000000..8b512e44f84
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i32-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e32m1,
+ vint32mf2_t,
+ vfloat64m1_t,
+ __riscv_vle32_v_i32mf2,
+ __riscv_vfwcvt_f_x_v_f64m1,
+ __riscv_vse64_v_f64m1,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c
new file mode 100644
index 00000000000..a38956e6fc0
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vint8m1_t,
+ vfloat16m2_t,
+ __riscv_vle8_v_i8m1,
+ __riscv_vfwcvt_f_x_v_f16m2,
+ __riscv_vse16_v_f16m2,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} 1 } }
*/
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c
new file mode 100644
index 00000000000..e2df3a7832f
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m2,
+ vint8m2_t,
+ vfloat16m4_t,
+ __riscv_vle8_v_i8m2,
+ __riscv_vfwcvt_f_x_v_f16m4,
+ __riscv_vse16_v_f16m4,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v2([^0-9]|$)} 1 } }
*/
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v4,v6} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c
new file mode 100644
index 00000000000..84eb453302c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m4,
+ vint8m4_t,
+ vfloat16m8_t,
+ __riscv_vle8_v_i8m4,
+ __riscv_vfwcvt_f_x_v_f16m8,
+ __riscv_vse16_v_f16m8,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v0,v4} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.x\.v\s+v8,v12} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c
new file mode 100644
index 00000000000..6614455b713
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vint8mf2_t,
+ vfloat16m1_t,
+ __riscv_vle8_v_i8mf2,
+ __riscv_vfwcvt_f_x_v_f16m1,
+ __riscv_vse16_v_f16m1,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c
new file mode 100644
index 00000000000..0c53407f92a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf4.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vint8mf4_t,
+ vfloat16mf2_t,
+ __riscv_vle8_v_i8mf4,
+ __riscv_vfwcvt_f_x_v_f16mf2,
+ __riscv_vse16_v_f16mf2,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c
new file mode 100644
index 00000000000..48f612851b2
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwcvt_f_x-i8-mf8.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+ __riscv_vsetvlmax_e8m1,
+ vint8mf8_t,
+ vfloat16mf4_t,
+ __riscv_vle8_v_i8mf8,
+ __riscv_vfwcvt_f_x_v_f16mf4,
+ __riscv_vse16_v_f16mf4,
+ vfwcvt_f_x,
+ LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v0,v1([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v2,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v4,v5} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v6,v7} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v8,v9} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v10,v11} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v12,v13} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v14,v15} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v16,v17} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v18,v19} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v20,v21} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v22,v23} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v24,v25} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v26,v27} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v28,v29} } } */
+/* { dg-final { scan-assembler-not {vfwcvt\.f\.x\.v\s+v30,v31} } } */
--
2.43.0
