AMD General Hi,
> -----Original Message----- > From: Jiang, Haochen <[email protected]> > Sent: 21 July 2026 12:00 > To: Sharma, Dipesh <[email protected]>; [email protected] > Cc: Liu, Hongtao <[email protected]>; [email protected]; > [email protected]; Kumar, Venkataramanan > <[email protected]> > Subject: RE: [PATCH v2 6/7] [X86]: Add FP8 to FP6 and vice-versa converts. > > Caution: This message originated from an External Source. Use proper > caution when opening attachments, clicking links, or responding. > > > > From: Dipesh Sharma <[email protected]> > > Sent: Monday, July 20, 2026 2:25 AM > > > > > > diff --git a/gcc/config/i386/avx10v2auxintrin.h > > b/gcc/config/i386/avx10v2auxintrin.h > > index bc004a24dfb..fd54af28857 100644 > > --- a/gcc/config/i386/avx10v2auxintrin.h > > +++ b/gcc/config/i386/avx10v2auxintrin.h > > @@ -1376,6 +1376,238 @@ _mm512_maskz_cvtbf4_hf8 (__mmask64 __U, > > __m256i __A) > > (__mmask64) __U); > > } > > > > +// VCVTBF82BF6S > > + > > +extern __inline __m128i > > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > > +_mm_cvtbf8_bf6s (__m128i __A) { > > + return (__m128i) __builtin_ia32_vcvtbf82bf6s128 ((__v16qi)__A); } > > + > > Similar for intrin issues. I will address it. > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > > dd6393cabf9..6fd38e9273b 100644 > > --- a/gcc/config/i386/sse.md > > +++ b/gcc/config/i386/sse.md > > @@ -34466,3 +34470,61 @@ > > + > > +(define_expand "vcvt<convertfp82fp6><mode>" > > + [(set (match_operand:AUXFP6CVT_MODE 0 "register_operand") > > + (vec_concat:AUXFP6CVT_MODE > > + (unspec:<fp82fp6_outmode> > > + [(match_operand:AUXFP6CVT_MODE 1 "register_operand")] > > + UNSPEC_CONVERTFP82FP6) > > + (match_dup 2)))] > > + "TARGET_AVX10V2AUX" > > + "operands[2] = CONST0_RTX (<fp82fp6_paddmode>mode);") > > + > > +(define_insn "*vcvt<convertfp82fp6><mode>" > > + [(set (match_operand:AUXFP6CVT_MODE 0 "register_operand" "=v") > > + (vec_concat:AUXFP6CVT_MODE > > + (unspec:<fp82fp6_outmode> > > + [(match_operand:AUXFP6CVT_MODE 1 "register_operand" "v")] > > + UNSPEC_CONVERTFP82FP6) > > + (match_operand:<fp82fp6_paddmode> 2 "const0_operand")))] > > + "TARGET_AVX10V2AUX" > > + "vcvt<convertfp82fp6>\t{%1, %0|%0, %1}" > > + [(set_attr "prefix" "evex") > > + (set_attr "mode" "<sseinsnmode>")]) > > It is overcomplicating the scenario. The reason we are zeroing is mainly > because of memory, while this is a register-only pattern. Also, FP6 is hard to > zero upper since it is stored consistently, which is not standard comparing to > the current bytewise structure. A pattern with UNSPEC is enough. ok > > Thx, > Haochen
