gcc/ChangeLog:
* config/i386/avx10v2auxintrin.h (_mm_cvtbf8_bf6s): New intrin.
(_mm256_cvtbf8_bf6s): Ditto.
(_mm512_cvtbf8_bf6s): Ditto.
(_mm_cvthf8_hf6s): Ditto.
(_mm256_cvthf8_hf6s): Ditto.
(_mm512_cvthf8_hf6s): Ditto.
(_mm_cvtbf6_hf8): Ditto.
(_mm_mask_cvtbf6_hf8): Ditto.
(_mm_maskz_cvtbf6_hf8): Ditto.
(_mm256_cvtbf6_hf8): Ditto.
(_mm256_mask_cvtbf6_hf8): Ditto.
(_mm256_maskz_cvtbf6_hf8): Ditto.
(_mm512_cvtbf6_hf8): Ditto.
(_mm512_mask_cvtbf6_hf8): Ditto.
(_mm512_maskz_cvtbf6_hf8): Ditto.
(_mm_cvthf6_hf8): Ditto.
(_mm_mask_cvthf6_hf8): Ditto.
(_mm_maskz_cvthf6_hf8): Ditto.
(_mm256_cvthf6_hf8): Ditto.
(_mm256_mask_cvthf6_hf8): Ditto.
(_mm256_maskz_cvthf6_hf8): Ditto.
(_mm512_cvthf6_hf8): Ditto.
(_mm512_mask_cvthf6_hf8): Ditto.
(_mm512_maskz_cvthf6_hf8): Ditto.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/i386-modes.def (VECTOR_MODE): New partial vector modes.
* config/i386/sse.md (vcvt<convertfp82fp6><mode>): New.
(*vcvt<convertfp82fp6><mode>): Ditto.
(vcvt<convertfp62hf8><mode><mask_name>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10v2aux-convert-1g.c: New test.
* gcc.target/i386/avx10v2aux-convert-1h.c: New test.
Co-authored-by: Venkataramanan Kumar <[email protected]>
Co-authored-by: Haochen Jiang <[email protected]>
---
gcc/config/i386/avx10v2auxintrin.h | 232 ++++++++++++++++++
gcc/config/i386/i386-builtin.def | 12 +
gcc/config/i386/i386-modes.def | 2 +
gcc/config/i386/sse.md | 62 +++++
.../gcc.target/i386/avx10v2aux-convert-1g.c | 18 ++
.../gcc.target/i386/avx10v2aux-convert-1h.c | 46 ++++
6 files changed, 372 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1g.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1h.c
diff --git a/gcc/config/i386/avx10v2auxintrin.h
b/gcc/config/i386/avx10v2auxintrin.h
index bc004a24dfb..fd54af28857 100644
--- a/gcc/config/i386/avx10v2auxintrin.h
+++ b/gcc/config/i386/avx10v2auxintrin.h
@@ -1376,6 +1376,238 @@ _mm512_maskz_cvtbf4_hf8 (__mmask64 __U, __m256i __A)
(__mmask64) __U);
}
+// VCVTBF82BF6S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf8_bf6s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf82bf6s128 ((__v16qi)__A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf8_bf6s (__m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf82bf6s256 ((__v32qi)__A);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf8_bf6s (__m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf82bf6s512 ((__v64qi)__A);
+}
+
+// VCVTHF82HF6S
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf8_hf6s (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf82hf6s128 ((__v16qi)__A);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf8_hf6s (__m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf82hf6s256 ((__v32qi)__A);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf8_hf6s (__m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvthf82hf6s512 ((__v64qi)__A);
+}
+
+// VCVTBF62HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbf6_hf8 (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf62hf8128_mask ((__v16qi)__A,
+ (__v16qi)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbf6_hf8 (__m128i __W, __mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf62hf8128_mask ((__v16qi)__A,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbf6_hf8 (__mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf62hf8128_mask ((__v16qi)__A,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBF62HF8 - 256-bit
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbf6_hf8 (__m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf62hf8256_mask ((__v32qi)__A,
+ (__v32qi)
+ _mm256_undefined_si256
(),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbf6_hf8 (__m256i __W, __mmask32 __U, __m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf62hf8256_mask ((__v32qi)__A,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbf6_hf8 (__mmask32 __U, __m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvtbf62hf8256_mask ((__v32qi)__A,
+ (__v32qi)
+ _mm256_setzero_si256 (),
+ (__mmask32) __U);
+}
+
+// VCVTBF62HF8 - 512-bit
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbf6_hf8 (__m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf62hf8512_mask ((__v64qi)__A,
+ (__v64qi)
+ _mm512_undefined_si512
(),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbf6_hf8 (__m512i __W, __mmask64 __U, __m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf62hf8512_mask ((__v64qi)__A,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbf6_hf8 (__mmask64 __U, __m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvtbf62hf8512_mask ((__v64qi)__A,
+ (__v64qi)
+ _mm512_setzero_si512 (),
+ (__mmask64) __U);
+}
+
+// VCVTHF62HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvthf6_hf8 (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf62hf8128_mask ((__v16qi)__A,
+ (__v16qi)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvthf6_hf8 (__m128i __W, __mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf62hf8128_mask ((__v16qi)__A,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvthf6_hf8 (__mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vcvthf62hf8128_mask ((__v16qi)__A,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTHF62HF8 - 256-bit
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvthf6_hf8 (__m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf62hf8256_mask ((__v32qi)__A,
+ (__v32qi)
+ _mm256_undefined_si256
(),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvthf6_hf8 (__m256i __W, __mmask32 __U, __m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf62hf8256_mask ((__v32qi)__A,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvthf6_hf8 (__mmask32 __U, __m256i __A)
+{
+ return (__m256i) __builtin_ia32_vcvthf62hf8256_mask ((__v32qi)__A,
+ (__v32qi)
+ _mm256_setzero_si256 (),
+ (__mmask32) __U);
+}
+
+// VCVTHF62HF8 - 512-bit
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvthf6_hf8 (__m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvthf62hf8512_mask ((__v64qi)__A,
+ (__v64qi)
+ _mm512_undefined_si512
(),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvthf6_hf8 (__m512i __W, __mmask64 __U, __m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvthf62hf8512_mask ((__v64qi)__A,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvthf6_hf8 (__mmask64 __U, __m512i __A)
+{
+ return (__m512i) __builtin_ia32_vcvthf62hf8512_mask ((__v64qi)__A,
+ (__v64qi)
+ _mm512_setzero_si512 (),
+ (__mmask64) __U);
+}
+
#ifdef __DISABLE_AVX10V2AUX__
#undef __DISABLE_AVX10V2AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 077565d3139..bc773c3b1ca 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3423,6 +3423,18 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_vcvthf82bf4sv64qi, "__builtin_ia
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v16qi_mask,
"__builtin_ia32_vcvtbf42hf8128_mask", IX86_BUILTIN_VCVTBF42HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v32qi_mask,
"__builtin_ia32_vcvtbf42hf8256_mask", IX86_BUILTIN_VCVTBF42HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_USI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf42hf8v64qi_mask,
"__builtin_ia32_vcvtbf42hf8512_mask", IX86_BUILTIN_VCVTBF42HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V32QI_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf6sv16qi,
"__builtin_ia32_vcvtbf82bf6s128", IX86_BUILTIN_VCVTBF82BF6S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf6sv32qi,
"__builtin_ia32_vcvtbf82bf6s256", IX86_BUILTIN_VCVTBF82BF6S256, UNKNOWN, (int)
V32QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf82bf6sv64qi,
"__builtin_ia32_vcvtbf82bf6s512", IX86_BUILTIN_VCVTBF82BF6S512, UNKNOWN, (int)
V64QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82hf6sv16qi,
"__builtin_ia32_vcvthf82hf6s128", IX86_BUILTIN_VCVTHF82HF6S128, UNKNOWN, (int)
V16QI_FTYPE_V16QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82hf6sv32qi,
"__builtin_ia32_vcvthf82hf6s256", IX86_BUILTIN_VCVTHF82HF6S256, UNKNOWN, (int)
V32QI_FTYPE_V32QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf82hf6sv64qi,
"__builtin_ia32_vcvthf82hf6s512", IX86_BUILTIN_VCVTHF82HF6S512, UNKNOWN, (int)
V64QI_FTYPE_V64QI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf62hf8v16qi_mask,
"__builtin_ia32_vcvtbf62hf8128_mask", IX86_BUILTIN_VCVTBF62HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf62hf8v32qi_mask,
"__builtin_ia32_vcvtbf62hf8256_mask", IX86_BUILTIN_VCVTBF62HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbf62hf8v64qi_mask,
"__builtin_ia32_vcvtbf62hf8512_mask", IX86_BUILTIN_VCVTBF62HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v16qi_mask,
"__builtin_ia32_vcvthf62hf8128_mask", IX86_BUILTIN_VCVTHF62HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v32qi_mask,
"__builtin_ia32_vcvthf62hf8256_mask", IX86_BUILTIN_VCVTHF62HF8256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvthf62hf8v64qi_mask,
"__builtin_ia32_vcvthf62hf8512_mask", IX86_BUILTIN_VCVTHF62HF8512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index ab672db4d75..2d87837b33b 100644
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -100,6 +100,8 @@ VECTOR_MODE (INT, SI, 1); /* V1SI */
VECTOR_MODE (INT, QI, 2); /* V2QI */
VECTOR_MODE (INT, QI, 12); /* V12QI */
VECTOR_MODE (INT, QI, 14); /* V14QI */
+VECTOR_MODE (INT, QI, 24); /* V24QI */
+VECTOR_MODE (INT, QI, 48); /* V48QI */
VECTOR_MODE (INT, HI, 6); /* V6HI */
INT_MODE (OI, 32);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index dd6393cabf9..6fd38e9273b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -275,6 +275,10 @@
UNSPEC_VCVTBF82BF4S
UNSPEC_VCVTHF82BF4S
UNSPEC_VCVTBF42HF8
+ UNSPEC_VCVTBF82BF6S
+ UNSPEC_VCVTHF82HF6S
+ UNSPEC_VCVTBF62HF8
+ UNSPEC_VCVTHF62HF8
])
(define_c_enum "unspecv" [
@@ -34466,3 +34470,61 @@
"vcvtbf42hf8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %<iptr_fp42fp8>1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+
+;; FP8 to FP6 converts (VCVTBF82BF6S, VCVTHF82HF6S) - no masking
+
+(define_int_iterator UNSPEC_CONVERTFP82FP6
+ [UNSPEC_VCVTBF82BF6S UNSPEC_VCVTHF82HF6S])
+
+(define_int_attr convertfp82fp6
+ [(UNSPEC_VCVTBF82BF6S "bf82bf6s")
+ (UNSPEC_VCVTHF82HF6S "hf82hf6s")])
+
+(define_mode_iterator AUXFP6CVT_MODE [V16QI V32QI V64QI])
+
+(define_mode_attr fp82fp6_outmode
+ [(V16QI "V12QI") (V32QI "V24QI") (V64QI "V48QI")])
+
+(define_mode_attr fp82fp6_paddmode
+ [(V16QI "V4QI") (V32QI "V8QI") (V64QI "V16QI")])
+
+(define_expand "vcvt<convertfp82fp6><mode>"
+ [(set (match_operand:AUXFP6CVT_MODE 0 "register_operand")
+ (vec_concat:AUXFP6CVT_MODE
+ (unspec:<fp82fp6_outmode>
+ [(match_operand:AUXFP6CVT_MODE 1 "register_operand")]
+ UNSPEC_CONVERTFP82FP6)
+ (match_dup 2)))]
+ "TARGET_AVX10V2AUX"
+ "operands[2] = CONST0_RTX (<fp82fp6_paddmode>mode);")
+
+(define_insn "*vcvt<convertfp82fp6><mode>"
+ [(set (match_operand:AUXFP6CVT_MODE 0 "register_operand" "=v")
+ (vec_concat:AUXFP6CVT_MODE
+ (unspec:<fp82fp6_outmode>
+ [(match_operand:AUXFP6CVT_MODE 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP82FP6)
+ (match_operand:<fp82fp6_paddmode> 2 "const0_operand")))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp82fp6>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+;; FP6 to FP8 converts (VCVTBF62HF8, VCVTHF62HF8) with masking
+
+(define_int_iterator UNSPEC_CONVERTFP62HF8
+ [UNSPEC_VCVTBF62HF8 UNSPEC_VCVTHF62HF8])
+
+(define_int_attr convertfp62hf8
+ [(UNSPEC_VCVTBF62HF8 "bf62hf8")
+ (UNSPEC_VCVTHF62HF8 "hf62hf8")])
+
+(define_insn "vcvt<convertfp62hf8><mode><mask_name>"
+ [(set (match_operand:AUXFP6CVT_MODE 0 "register_operand" "=v")
+ (unspec:AUXFP6CVT_MODE
+ [(match_operand:AUXFP6CVT_MODE 1 "register_operand" "v")]
+ UNSPEC_CONVERTFP62HF8))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<convertfp62hf8>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1g.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1g.c
new file mode 100644
index 00000000000..ad34848a462
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1g.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf6s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf6s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf82bf6s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82hf6s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82hf6s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf82hf6s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m128i test_mm_cvtbf8_bf6s (__m128i a) { return _mm_cvtbf8_bf6s (a); }
+__m256i test_mm256_cvtbf8_bf6s (__m256i a) { return _mm256_cvtbf8_bf6s (a); }
+__m512i test_mm512_cvtbf8_bf6s (__m512i a) { return _mm512_cvtbf8_bf6s (a); }
+
+__m128i test_mm_cvthf8_hf6s (__m128i a) { return _mm_cvthf8_hf6s (a); }
+__m256i test_mm256_cvthf8_hf6s (__m256i a) { return _mm256_cvthf8_hf6s (a); }
+__m512i test_mm512_cvthf8_hf6s (__m512i a) { return _mm512_cvthf8_hf6s (a); }
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1h.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1h.c
new file mode 100644
index 00000000000..4e591e63ae0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1h.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2" } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvthf62hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m128i test_mm_cvtbf6_hf8 (__m128i a) { return _mm_cvtbf6_hf8 (a); }
+__m128i test_mm_mask_cvtbf6_hf8 (__m128i w, __mmask16 u, __m128i a) { return
_mm_mask_cvtbf6_hf8 (w, u, a); }
+__m128i test_mm_maskz_cvtbf6_hf8 (__mmask16 u, __m128i a) { return
_mm_maskz_cvtbf6_hf8 (u, a); }
+
+__m256i test_mm256_cvtbf6_hf8 (__m256i a) { return _mm256_cvtbf6_hf8 (a); }
+__m256i test_mm256_mask_cvtbf6_hf8 (__m256i w, __mmask32 u, __m256i a) {
return _mm256_mask_cvtbf6_hf8 (w, u, a); }
+__m256i test_mm256_maskz_cvtbf6_hf8 (__mmask32 u, __m256i a) { return
_mm256_maskz_cvtbf6_hf8 (u, a); }
+
+__m512i test_mm512_cvtbf6_hf8 (__m512i a) { return _mm512_cvtbf6_hf8 (a); }
+__m512i test_mm512_mask_cvtbf6_hf8 (__m512i w, __mmask64 u, __m512i a) {
return _mm512_mask_cvtbf6_hf8 (w, u, a); }
+__m512i test_mm512_maskz_cvtbf6_hf8 (__mmask64 u, __m512i a) { return
_mm512_maskz_cvtbf6_hf8 (u, a); }
+
+__m128i test_mm_cvthf6_hf8 (__m128i a) { return _mm_cvthf6_hf8 (a); }
+__m128i test_mm_mask_cvthf6_hf8 (__m128i w, __mmask16 u, __m128i a) { return
_mm_mask_cvthf6_hf8 (w, u, a); }
+__m128i test_mm_maskz_cvthf6_hf8 (__mmask16 u, __m128i a) { return
_mm_maskz_cvthf6_hf8 (u, a); }
+
+__m256i test_mm256_cvthf6_hf8 (__m256i a) { return _mm256_cvthf6_hf8 (a); }
+__m256i test_mm256_mask_cvthf6_hf8 (__m256i w, __mmask32 u, __m256i a) {
return _mm256_mask_cvthf6_hf8 (w, u, a); }
+__m256i test_mm256_maskz_cvthf6_hf8 (__mmask32 u, __m256i a) { return
_mm256_maskz_cvthf6_hf8 (u, a); }
+
+__m512i test_mm512_cvthf6_hf8 (__m512i a) { return _mm512_cvthf6_hf8 (a); }
+__m512i test_mm512_mask_cvthf6_hf8 (__m512i w, __mmask64 u, __m512i a) {
return _mm512_mask_cvthf6_hf8 (w, u, a); }
+__m512i test_mm512_maskz_cvthf6_hf8 (__mmask64 u, __m512i a) { return
_mm512_maskz_cvthf6_hf8 (u, a); }
--
2.34.1
