gcc/ChangeLog:
* config/i386/avx10v2auxintrin.h (_mm_cvtbiasps_bf8): New intrin.
(_mm_mask_cvtbiasps_bf8): Ditto.
(_mm_maskz_cvtbiasps_bf8): Ditto.
(_mm256_cvtbiasps_bf8): Ditto.
(_mm256_mask_cvtbiasps_bf8): Ditto.
(_mm256_maskz_cvtbiasps_bf8): Ditto.
(_mm512_cvtbiasps_bf8): Ditto.
(_mm512_mask_cvtbiasps_bf8): Ditto.
(_mm512_maskz_cvtbiasps_bf8): Ditto.
(_mm_cvts_biasps_bf8): Ditto.
(_mm_mask_cvts_biasps_bf8): Ditto.
(_mm_maskz_cvts_biasps_bf8): Ditto.
(_mm256_cvts_biasps_bf8): Ditto.
(_mm256_mask_cvts_biasps_bf8): Ditto.
(_mm256_maskz_cvts_biasps_bf8): Ditto.
(_mm512_cvts_biasps_bf8): Ditto.
(_mm512_mask_cvts_biasps_bf8): Ditto.
(_mm512_maskz_cvts_biasps_bf8): Ditto.
(_mm_cvtbiasps_hf8): Ditto.
(_mm_mask_cvtbiasps_hf8): Ditto.
(_mm_maskz_cvtbiasps_hf8): Ditto.
(_mm256_cvtbiasps_hf8): Ditto.
(_mm256_mask_cvtbiasps_hf8): Ditto.
(_mm256_maskz_cvtbiasps_hf8): Ditto.
(_mm512_cvtbiasps_hf8): Ditto.
(_mm512_mask_cvtbiasps_hf8): Ditto.
(_mm512_maskz_cvtbiasps_hf8): Ditto.
(_mm_cvts_biasps_hf8): Ditto.
(_mm_mask_cvts_biasps_hf8): Ditto.
(_mm_maskz_cvts_biasps_hf8): Ditto.
(_mm256_cvts_biasps_hf8): Ditto.
(_mm256_mask_cvts_biasps_hf8): Ditto.
(_mm256_maskz_cvts_biasps_hf8): Ditto.
(_mm512_cvts_biasps_hf8): Ditto.
(_mm512_mask_cvts_biasps_hf8): Ditto.
(_mm512_maskz_cvts_biasps_hf8): Ditto.
* config/i386/i386-builtin-types.def (V16QI): New funtion types.
* config/i386/i386-builtin.def (BDESC): New builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle new
function types.
* config/i386/sse.md (vcvt<biasps2fp8><mode>): New.
(*vcvt<biasps2fp8><mode>): Ditto.
(vcvt<biasps2fp8>v4sf_mask): Ditto.
(*vcvt<biasps2fp8>v4sf_mask): Ditto.
(vcvt<biasps2fp8>v8sf_mask): Ditto.
(*vcvt<biasps2fp8>v8sf_mask): Ditto.
(vcvt<biasps2fp8>v16sf<mask_name>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10v2aux-convert-1c.c: New test.
Co-authored-by: Venkataramanan Kumar <[email protected]>
Co-authored-by: Haochen Jiang <[email protected]>
---
gcc/config/i386/avx10v2auxintrin.h | 421 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 12 +
gcc/config/i386/i386-expand.cc | 3 +
gcc/config/i386/sse.md | 131 ++++++
.../gcc.target/i386/avx10v2aux-convert-1c.c | 114 +++++
6 files changed, 684 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1c.c
diff --git a/gcc/config/i386/avx10v2auxintrin.h
b/gcc/config/i386/avx10v2auxintrin.h
index 3183052b3a3..d67556352cc 100644
--- a/gcc/config/i386/avx10v2auxintrin.h
+++ b/gcc/config/i386/avx10v2auxintrin.h
@@ -587,6 +587,427 @@ _mm512_maskz_cvts_rops_hf8 (__mmask16 __U, __m512 __A)
(__mmask16) __U);
}
+// VCVTBIASPS2BF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbiasps_bf8 (__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)(__m128i)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbiasps_bf8 (__m128i __W, __mmask8 __U,
+ __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbiasps_bf8 (__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)(__m128i)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8 - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbiasps_bf8 (__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbiasps_bf8 (__m128i __W, __mmask8 __U,
+ __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbiasps_bf8 (__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8 - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbiasps_bf8 (__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbiasps_bf8 (__m128i __W, __mmask16 __U,
+ __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbiasps_bf8 (__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2BF8S - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasps_bf8 (__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvts_biasps_bf8 (__m128i __W, __mmask8 __U,
+ __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvts_biasps_bf8 (__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8S - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasps_bf8 (__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvts_biasps_bf8 (__m128i __W, __mmask8 __U,
+ __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvts_biasps_bf8 (__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2BF8S - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasps_bf8 (__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvts_biasps_bf8 (__m128i __W, __mmask16 __U,
+ __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvts_biasps_bf8 (__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2bf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2HF8 - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvtbiasps_hf8 (__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvtbiasps_hf8 (__m128i __W, __mmask8 __U,
+ __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvtbiasps_hf8 (__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8 - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvtbiasps_hf8 (__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvtbiasps_hf8 (__m128i __W, __mmask8 __U,
+ __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvtbiasps_hf8 (__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8 - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvtbiasps_hf8 (__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvtbiasps_hf8 (__m128i __W, __mmask16 __U,
+ __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvtbiasps_hf8 (__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+// VCVTBIASPS2HF8S - 128-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasps_hf8 (__m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_cvts_biasps_hf8 (__m128i __W, __mmask8 __U,
+ __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_cvts_biasps_hf8 (__mmask8 __U, __m128i __A, __m128 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s128_mask ((__v4si) __A,
+ (__v4sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8S - 256-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasps_hf8 (__m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_cvts_biasps_hf8 (__m128i __W, __mmask8 __U,
+ __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_cvts_biasps_hf8 (__mmask8 __U, __m256i __A, __m256 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s256_mask ((__v8si) __A,
+ (__v8sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+// VCVTBIASPS2HF8S - 512-bit
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasps_hf8 (__m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_undefined_si128
(),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_cvts_biasps_hf8 (__m128i __W, __mmask16 __U,
+ __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_cvts_biasps_hf8 (__mmask16 __U, __m512i __A, __m512 __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasps2hf8s512_mask ((__v16si) __A,
+ (__v16sf) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
#ifdef __DISABLE_AVX10V2AUX__
#undef __DISABLE_AVX10V2AUX__
#pragma GCC pop_options
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index 34e0cf7f8d3..b53219c9aa8 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1478,6 +1478,9 @@ DEF_FUNCTION_TYPE (V8SI, V8DF, V8SI, UQI)
DEF_FUNCTION_TYPE (V16QI, V4SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V8SF, V16QI, UQI)
DEF_FUNCTION_TYPE (V16QI, V16SF, V16QI, UHI)
+DEF_FUNCTION_TYPE (V16QI, V4SI, V4SF, V16QI, UQI)
+DEF_FUNCTION_TYPE (V16QI, V8SI, V8SF, V16QI, UQI)
+DEF_FUNCTION_TYPE (V16QI, V16SI, V16SF, V16QI, UHI)
# SM4 builtins
DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index e20a21aec1c..db10e6fe351 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3388,6 +3388,18 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_vcvtrops2hf8v16sf_mask, "__built
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv4sf_mask,
"__builtin_ia32_vcvtrops2hf8s128_mask", IX86_BUILTIN_VCVTROPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv8sf_mask,
"__builtin_ia32_vcvtrops2hf8s256_mask", IX86_BUILTIN_VCVTROPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SF_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtrops2hf8sv16sf_mask,
"__builtin_ia32_vcvtrops2hf8s512_mask", IX86_BUILTIN_VCVTROPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8v4sf_mask,
"__builtin_ia32_vcvtbiasps2bf8128_mask", IX86_BUILTIN_VCVTBIASPS2BF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8v8sf_mask,
"__builtin_ia32_vcvtbiasps2bf8256_mask", IX86_BUILTIN_VCVTBIASPS2BF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8v16sf_mask,
"__builtin_ia32_vcvtbiasps2bf8512_mask", IX86_BUILTIN_VCVTBIASPS2BF8512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s128_mask", IX86_BUILTIN_VCVTBIASPS2BF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s256_mask", IX86_BUILTIN_VCVTBIASPS2BF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2bf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2bf8s512_mask", IX86_BUILTIN_VCVTBIASPS2BF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8v4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8128_mask", IX86_BUILTIN_VCVTBIASPS2HF8128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8v8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8256_mask", IX86_BUILTIN_VCVTBIASPS2HF8256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8v16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8512_mask", IX86_BUILTIN_VCVTBIASPS2HF8512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SI_V16SF_V16QI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv4sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s128_mask", IX86_BUILTIN_VCVTBIASPS2HF8S128_MASK,
UNKNOWN, (int) V16QI_FTYPE_V4SI_V4SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv8sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s256_mask", IX86_BUILTIN_VCVTBIASPS2HF8S256_MASK,
UNKNOWN, (int) V16QI_FTYPE_V8SI_V8SF_V16QI_UQI)
+BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX, CODE_FOR_vcvtbiasps2hf8sv16sf_mask,
"__builtin_ia32_vcvtbiasps2hf8s512_mask", IX86_BUILTIN_VCVTBIASPS2HF8S512_MASK,
UNKNOWN, (int) V16QI_FTYPE_V16SI_V16SF_V16QI_UHI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 9acf24031f2..c85417943b9 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -13225,6 +13225,9 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16QI_FTYPE_V16QI_V8HF_V16QI_UHI:
case V16QI_FTYPE_V32QI_V16HF_V16QI_UHI:
case V32QI_FTYPE_V64QI_V32HF_V32QI_USI:
+ case V16QI_FTYPE_V4SI_V4SF_V16QI_UQI:
+ case V16QI_FTYPE_V8SI_V8SF_V16QI_UQI:
+ case V16QI_FTYPE_V16SI_V16SF_V16QI_UHI:
nargs = 4;
break;
case V2DF_FTYPE_V2DF_V2DF_V2DI_INT:
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 742c013d14f..234acd7aa21 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -266,6 +266,10 @@
UNSPEC_VCVTPS2HF8S
UNSPEC_VCVTROPS2HF8
UNSPEC_VCVTROPS2HF8S
+ UNSPEC_VCVTBIASPS2BF8
+ UNSPEC_VCVTBIASPS2BF8S
+ UNSPEC_VCVTBIASPS2HF8
+ UNSPEC_VCVTBIASPS2HF8S
])
(define_c_enum "unspecv" [
@@ -34221,3 +34225,130 @@
"vcvt<convertps2fp8>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "prefix" "evex")
(set_attr "mode" "V16SF")])
+
+;; FP32 to FP8 biased converts (VCVTBIASPS2BF8, VCVTBIASPS2BF8S,
+;; VCVTBIASPS2HF8, VCVTBIASPS2HF8S)
+
+(define_int_iterator UNSPEC_CONVERTBIASPS2FP8
+ [UNSPEC_VCVTBIASPS2BF8 UNSPEC_VCVTBIASPS2BF8S
+ UNSPEC_VCVTBIASPS2HF8 UNSPEC_VCVTBIASPS2HF8S])
+
+(define_int_attr biasps2fp8
+ [(UNSPEC_VCVTBIASPS2BF8 "biasps2bf8")
+ (UNSPEC_VCVTBIASPS2BF8S "biasps2bf8s")
+ (UNSPEC_VCVTBIASPS2HF8 "biasps2hf8")
+ (UNSPEC_VCVTBIASPS2HF8S "biasps2hf8s")])
+
+(define_mode_attr ps2fp8biasmode
+ [(V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")])
+
+(define_expand "vcvt<biasps2fp8><mode>"
+ [(set (match_operand:V16QI 0 "register_operand")
+ (vec_concat:V16QI
+ (unspec:<ps2fp8outmode>
+ [(match_operand:<ps2fp8biasmode> 1 "register_operand")
+ (match_operand:VPS2FP8_PART 2 "nonimmediate_operand")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (match_dup 3)))]
+ "TARGET_AVX10V2AUX"
+ "operands[3] = CONST0_RTX (<ps2fp8padmode>mode);")
+
+(define_insn "*vcvt<biasps2fp8><mode>"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (unspec:<ps2fp8outmode>
+ [(match_operand:<ps2fp8biasmode> 1 "register_operand" "v")
+ (match_operand:VPS2FP8_PART 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (match_operand:<ps2fp8padmode> 3 "const0_operand")))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<biasps2fp8>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<MODE>")])
+
+(define_expand "vcvt<biasps2fp8>v4sf_mask"
+ [(set (match_operand:V16QI 0 "register_operand")
+ (vec_concat:V16QI
+ (vec_merge:V4QI
+ (unspec:V4QI
+ [(match_operand:V4SI 1 "register_operand")
+ (match_operand:V4SF 2 "nonimmediate_operand")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (vec_select:V4QI
+ (match_operand:V16QI 3 "nonimm_or_0_operand")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))
+ (match_operand:QI 4 "register_operand" "C"))
+ (match_dup 5)))]
+ "TARGET_AVX10V2AUX"
+ "operands[5] = CONST0_RTX (V12QImode);")
+
+(define_insn "*vcvt<biasps2fp8>v4sf_mask"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V4QI
+ (unspec:V4QI
+ [(match_operand:V4SI 1 "register_operand" "v")
+ (match_operand:V4SF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (vec_select:V4QI
+ (match_operand:V16QI 3 "nonimm_or_0_operand" "0C")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)]))
+ (match_operand:QI 4 "register_operand" "Yk"))
+ (match_operand:V12QI 5 "const0_operand")))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<biasps2fp8>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "V4SF")])
+
+(define_expand "vcvt<biasps2fp8>v8sf_mask"
+ [(set (match_operand:V16QI 0 "register_operand")
+ (vec_concat:V16QI
+ (vec_merge:V8QI
+ (unspec:V8QI
+ [(match_operand:V8SI 1 "register_operand")
+ (match_operand:V8SF 2 "nonimmediate_operand")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (vec_select:V8QI
+ (match_operand:V16QI 3 "nonimm_or_0_operand")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)
+ (const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)]))
+ (match_operand:QI 4 "register_operand" "C"))
+ (match_dup 5)))]
+ "TARGET_AVX10V2AUX"
+ "operands[5] = CONST0_RTX (V8QImode);")
+
+(define_insn "*vcvt<biasps2fp8>v8sf_mask"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (vec_concat:V16QI
+ (vec_merge:V8QI
+ (unspec:V8QI
+ [(match_operand:V8SI 1 "register_operand" "v")
+ (match_operand:V8SF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8)
+ (vec_select:V8QI
+ (match_operand:V16QI 3 "nonimm_or_0_operand" "0C")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)
+ (const_int 4) (const_int 5)
+ (const_int 6) (const_int 7)]))
+ (match_operand:QI 4 "register_operand" "Yk"))
+ (match_operand:V8QI 5 "const0_operand")))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<biasps2fp8>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "V8SF")])
+
+(define_insn "vcvt<biasps2fp8>v16sf<mask_name>"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:V16SI 1 "register_operand" "v")
+ (match_operand:V16SF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_CONVERTBIASPS2FP8))]
+ "TARGET_AVX10V2AUX"
+ "vcvt<biasps2fp8>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "V16SF")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1c.c
b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1c.c
new file mode 100644
index 00000000000..cb28447b050
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10v2aux-convert-1c.c
@@ -0,0 +1,114 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10v2aux -O2 -fno-fuse-ops-with-volatile-access" } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2bf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%ymm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasps2hf8s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%zmm\[0-9\]+,\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 a1;
+volatile __m256 a2;
+volatile __m512 a3;
+volatile __m128i b1;
+volatile __m256i b2;
+volatile __m512i b3;
+volatile __m128i x128i;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+
+void extern
+avx10v2aux_vcvtbiasps2bf8_test (void)
+{
+ x128i = _mm_cvtbiasps_bf8 (b1, a1);
+ x128i = _mm_mask_cvtbiasps_bf8 (x128i, m8, b1, a1);
+ x128i = _mm_maskz_cvtbiasps_bf8 (m8, b1, a1);
+
+ x128i = _mm256_cvtbiasps_bf8 (b2, a2);
+ x128i = _mm256_mask_cvtbiasps_bf8 (x128i, m8, b2, a2);
+ x128i = _mm256_maskz_cvtbiasps_bf8 (m8, b2, a2);
+
+ x128i = _mm512_cvtbiasps_bf8 (b3, a3);
+ x128i = _mm512_mask_cvtbiasps_bf8 (x128i, m16, b3, a3);
+ x128i = _mm512_maskz_cvtbiasps_bf8 (m16, b3, a3);
+}
+
+void extern
+avx10v2aux_vcvtbiasps2bf8s_test (void)
+{
+ x128i = _mm_cvts_biasps_bf8 (b1, a1);
+ x128i = _mm_mask_cvts_biasps_bf8 (x128i, m8, b1, a1);
+ x128i = _mm_maskz_cvts_biasps_bf8 (m8, b1, a1);
+
+ x128i = _mm256_cvts_biasps_bf8 (b2, a2);
+ x128i = _mm256_mask_cvts_biasps_bf8 (x128i, m8, b2, a2);
+ x128i = _mm256_maskz_cvts_biasps_bf8 (m8, b2, a2);
+
+ x128i = _mm512_cvts_biasps_bf8 (b3, a3);
+ x128i = _mm512_mask_cvts_biasps_bf8 (x128i, m16, b3, a3);
+ x128i = _mm512_maskz_cvts_biasps_bf8 (m16, b3, a3);
+}
+
+void extern
+avx10v2aux_vcvtbiasps2hf8_test (void)
+{
+ x128i = _mm_cvtbiasps_hf8 (b1, a1);
+ x128i = _mm_mask_cvtbiasps_hf8 (x128i, m8, b1, a1);
+ x128i = _mm_maskz_cvtbiasps_hf8 (m8, b1, a1);
+
+ x128i = _mm256_cvtbiasps_hf8 (b2, a2);
+ x128i = _mm256_mask_cvtbiasps_hf8 (x128i, m8, b2, a2);
+ x128i = _mm256_maskz_cvtbiasps_hf8 (m8, b2, a2);
+
+ x128i = _mm512_cvtbiasps_hf8 (b3, a3);
+ x128i = _mm512_mask_cvtbiasps_hf8 (x128i, m16, b3, a3);
+ x128i = _mm512_maskz_cvtbiasps_hf8 (m16, b3, a3);
+}
+
+void extern
+avx10v2aux_vcvtbiasps2hf8s_test (void)
+{
+ x128i = _mm_cvts_biasps_hf8 (b1, a1);
+ x128i = _mm_mask_cvts_biasps_hf8 (x128i, m8, b1, a1);
+ x128i = _mm_maskz_cvts_biasps_hf8 (m8, b1, a1);
+
+ x128i = _mm256_cvts_biasps_hf8 (b2, a2);
+ x128i = _mm256_mask_cvts_biasps_hf8 (x128i, m8, b2, a2);
+ x128i = _mm256_maskz_cvts_biasps_hf8 (m8, b2, a2);
+
+ x128i = _mm512_cvts_biasps_hf8 (b3, a3);
+ x128i = _mm512_mask_cvts_biasps_hf8 (x128i, m16, b3, a3);
+ x128i = _mm512_maskz_cvts_biasps_hf8 (m16, b3, a3);
+}
--
2.34.1
