On 8/24/26 12:20 AM, wangjue wrote:
From: juewang <[email protected]>
seq_cost treats every instruction in a replacement sequence as serial.
This can overestimate simple register-only sequences on superscalar
targets and reject profitable if-conversion.
Build dependency levels for simple, unit-cost register operations.
Cost each level using the target issue rate. Fall back to the serial
cost for unsupported sequences, size optimization, and targets without
an issue rate hook.
Changes since v1:
v3: Refactor instruction validation and dependency-level calculation into
separate helpers. Add comments explaining the intent of the parallel cost
model.
v2: Guard against calling targetm.sched.issue_rate when the hook is not
defined.
gcc/ChangeLog:
* ifcvt.cc (noce_parallel_cost_node): New.
(noce_parallel_costed_insn_p): New.
(noce_dependency_level): New.
(noce_parallel_seq_cost): New.
(default_noce_conversion_profitable_p): Use it.
---
gcc/ifcvt.cc | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 5ea25f8fbe7..b458b0db253 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -803,6 +803,108 @@ noce_reversed_cond_code (struct noce_if_info *if_info)
return reversed_comparison_code (if_info->cond, if_info->jump);
}
+/* A register definition and its dependency level. */
+
+struct noce_parallel_cost_node
+{
+ rtx dest;
+ unsigned int level;
+};
+
+/* Return true if INSN is a unit-cost register SET supported by the parallel
+ cost model. Store the SET in *SET. */
+
+static bool
+noce_parallel_costed_insn_p (rtx_insn *insn, bool speed_p, rtx *set)
+{
+ *set = single_set (insn);
+ if (!*set)
+ return false;
+
+ rtx dest = SET_DEST (*set);
+ rtx src = SET_SRC (*set);
+
+ return REG_P (dest)
+ && !contains_mem_rtx_p (src)
+ && !side_effects_p (src)
+ && !may_trap_p (src)
+ && set_rtx_cost (*set, speed_p) == COSTS_N_INSNS (1);
Style nit. On a multi-line conditional put the conditional in a
parenthesis pair. Indent the additional lines just inside the paren.
ie like this:
if (a
&& b
&& c)
Implementation details are fine. Given this potentially impacts every
target GCC supports, the bare minimum testing would be verification that
x86 or aarch64 will bootstrap and regression test successfully. Please
take care of that testing. I'll do some testing on the crosses.
Depending on what we find there may be testsuite adjustments to make
before committing.
Even with the x86/aarch64 and cross testing, we could still easily see
failures on other targets like s390x, ppc and such. So we'll have to
keep a close eye on bugzilla once we do commit the chnage.
Jeff
