On Wednesday 03 December 2008, Stephen Williams wrote:
> Svenn Are Bjerkem wrote:
> > Why can't some funding flow into some of the tools
> > available to make that -A/MS happen?
> > Icarus, GHDL, freehdl, ngspice and gnucap are all tools
> > that are in use, but none of them really support the
> > concept of A/MS (yet) in the Verilog/VHDL-AMS concept.
> > Until that happens lots of money has to be spent to be able
> > to do "real" AMS
>
> Icarus Verilog is working on Verilog-A/MS support, but
> funding is always welcomed;-)
>
> There is enough support in the core compiler that someone who
> has gnucap and Icarus Verilog skills can start looking at
> integration at the code generator level. For example, there
> is no reason that Icarus Verilog can't be used as a Verilog-A
> that generates gnucap simulations.

Steve beat me to it...

There is effort in both gnucap and icarus to do this.

On the gnucap side, the development snapshot accepts netlists in 
Verilog format now.  (and Spectre too)  Gnucap will directly 
accept all of the structural subset, and a substantial part of 
the analog extensions, interactively.

Through plugins, gnucap accepts external models in a variety of 
formats.  The snapshot already accepts C models written for 
Spice, in several variants.

On the Icarus side, the effort is toward being able to compile 
Verilog-AMS into C code (or C++) modules.  These modules will 
be used by gnucap as plugins.

There is also work toward accepting System-C modules as gnucap 
plugins.  This is likely to happen fairly soon.  It is a 
wrapper, so it should be fairly easy.  The System-C interface 
appears to be much better designed than the Spice interface, so 
it should be easy by comparison.



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