Svenn Are Bjerkem wrote:

>> I wonder what tools Paul Horowitz uses these days. *There's* a guy
>> who understands mixed signal disign and can write clearly about it.
> 
> Are you thinking of "Art of electronics"? or any other book by him? I
> don't think I have access to the papers he has published on IEEE. Have
> to pay to download pdf.

That would be "paper" (singular, not plural).  As near as I can tell the 
IEEE is not his forum for publication aside from a CICS conference paper 
from a few years back.  But unless his group is run differently than 
most, it was his students paper anyway.  It was a pretty cool paper 
about a chip designed to solve a really cool problem.  But.... the chip 
was designed by the student at *stanford* and not harvard.  It sounds 
like he (the student) went to Stanford not as a student there but to 
collaborate with some circuit design students out there to be able to 
get the chip design done.  On top of that rev 1 was non-functional (not 
that it wasn't meeting spec, but functional problems that prevented 
testing of the chip).  At least one should have been caught using modern 
timing analysis or timing back annotation into a verilog sim.  The other 
was a power ground connection problem that is all to easy to do when you 
simulate your blocks with spice but don't do a full chip simulation.... 
  Yes, I wonder what tools they used or didn't use.

In all fairness, academic chips *never* undergo the full set of 
simulations that they should because typically you have a single novice 
designer doing the job of an experienced design team and either because 
of lack of experience with the tools or simply no more time before 
funding runs out, a design goes out before it is really production 
ready.  So I certainly don't mean this as a knock against the student. 
Still, bugs like that (i.e. the chip is non-functional enough that you 
can't really even test it) in a company would have been tough to explain.


-Dan






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