Here is the 'verilogXL' output of these two files:
shaun:/home/shaun/stephen> verilog nblkpush.v
Tool: VERILOG-XL 05.40.003-s Jun 27, 2005 14:25:25
Copyright (c) 1995-2004 Cadence Design Systems, Inc. All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.
Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with
Permission.
THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.
Cadence Design Systems, Inc.
555 River Oaks Parkway
San Jose, California 95134
For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to [EMAIL PROTECTED]
For more information on Cadence's Verilog-XL product line send email to
[EMAIL PROTECTED]
Compiling source file "nblkpush.v"
Highest level modules:
test
PASSED
L41 "nblkpush.v": $finish at simulation time 1
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in simulation
End of Tool: VERILOG-XL 05.40.003-s Jun 27, 2005 14:25:27
shaun:/home/shaun/stephen> verilog sched2.v
Tool: VERILOG-XL 05.40.003-s Jun 27, 2005 14:26:28
Copyright (c) 1995-2004 Cadence Design Systems, Inc. All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.
Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with
Permission.
THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC. USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.
Cadence Design Systems, Inc.
555 River Oaks Parkway
San Jose, California 95134
For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to [EMAIL PROTECTED]
For more information on Cadence's Verilog-XL product line send email to
[EMAIL PROTECTED]
Compiling source file "sched2.v"
Highest level modules:
main
FAILED -- q changed too soon? 1
L41 "sched2.v": $finish at simulation time 1
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool: VERILOG-XL 05.40.003-s Jun 27, 2005 14:26:28
and the 'ncverilog' output - the results are reversed from 'verilogXL' !!
shaun:/home/shaun/stephen> ncverilog nblkpush.v
ncverilog: 05.40-s009: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
file: nblkpush.v
module worklib.test:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.test:v <0x6ff125bc>
streams: 4, words: 401
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 4 4
Scalar wires: 3 -
Initial blocks: 1 1
Cont. assignments: 3 3
Writing initial simulation snapshot: worklib.test:v
Loading snapshot worklib.test:v .................... Done
ncsim> source /usr/ldv/tools/inca/files/ncsimrc
ncsim> run
FAILED ab=0, abc=0, abcd=0
abcd value changed late
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
shaun:/home/shaun/stephen> ncverilog sched2.v
ncverilog: 05.40-s009: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
file: sched2.v
module worklib.main:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.main:v <0x3359110b>
streams: 2, words: 352
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Registers: 2 2
Scalar wires: 1 -
Initial blocks: 1 1
Cont. assignments: 1 1
Writing initial simulation snapshot: worklib.main:v
Loading snapshot worklib.main:v .................... Done
ncsim> source /usr/ldv/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Interesting results !!
Stephen.
