> From - Mon Jun 27 20:56:39 PDT 2005 > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > > Ugh, New Cadence and Old Cadence don't agree with each other. ncverilog > seems to match Modelsim, but VCS gets something else altogether. I've > opened a sticky can of worms here. Currently, Icarus Verilog 0.8 and > CVS main trunk match ncverilog and Modelsim. I guess that's what I'll > stick with for now.
Since the tests seem to be using blocking rather than non-blocking assigns there really shouldn't be a scheduling issue - i.e. blocking assigns should just be executed immediately rather than scheduled, so the Verilog-XL looks like the right behavior to me. The comment in sched2.v about the "& gate" is bogus because there is no and gate only a logical operation (with no delay), and the LRM says the LHS is assigned when the RHS changes for a continuous assign. >From a performance perspective you don't want to schedule anything if you don't have to since that's extra overhead - so the XL behavior is preferable. Also, spliting the assignment over delta cycles (or at least making it non-atomic) is more likely to cause race conditions. > It's not unreasonable for there to be valid differences here, as the > standard is not explicit on this particular scheduling issue. Actually it's pretty unreasonable that there is such a disparity on these simple cases. I think there is a problem in that there is no official "reference" simulator to defer to for the "correct" result - an exercise for someone in academia perhaps. Kev. > Stephen Brickles wrote: > | Here is the 'verilogXL' output of these two files: > > | Compiling source file "nblkpush.v" > | Highest level modules: > | test > | > | PASSED > > > > | Compiling source file "sched2.v" > | Highest level modules: > | main > | > | FAILED -- q changed too soon? 1 > > > | and the 'ncverilog' output - the results are reversed from 'verilogXL' !! > | > | shaun:/home/shaun/stephen> ncverilog nblkpush.v > | ncverilog: 05.40-s009: (c) Copyright 1995-2005 Cadence Design Systems, Inc. > > | FAILED ab=0, abc=0, abcd=0 > | abcd value changed late > | ncsim: *W,RNQUIE: Simulation is complete. > > > | shaun:/home/shaun/stephen> ncverilog sched2.v > > | PASSED > > > > - -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.2.5 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > > iD8DBQFCwHbgrPt1Sc2b3ikRAsNgAKCQRqj8UqaWHY0ucSzDbplCdUoT1wCfUwWp > 28dD5R5k9neoKVzCgCg8Q8g= > =3hkI > -----END PGP SIGNATURE----- >
