On Thursday 06 January 2005 11:15 am, John Dozsa wrote: > Consider adopting the > Mentor Graphics (MGC) Board Station ASCII database. �This has > become a defacto standard for many translators between high > end pcb tools.
I think we should adopt published standards, not vendor "standards". If this is a defacto standard, do you mean that Cadence, Synopsys, Protel, and others use it as their default? If no, then it isn't a defacto standard. Vendors do publish their formats to allow interoperability, but it is only standard if it is fully documented, competitors use it as they do, and even exert some control over it. If you look at real standards, such as IEEE or EIA standards, they are controlled by a committee. The committee consists of both users and tool suppliers. These committees are open to interested participants. If we want to, we can have a place on the committee. What I would like to see is for us to use a VHDL variant. VHDL defines "entity" and "architecture" blocks for synthesis and simulation. To make extensions for layout and schematic, add new top level blocks to contain the extra information: We have: entity ().... is like a C function prototype architecture () .... describes how it actually works. There can be more than one. Now add: layout ()... describes layout information schematic ()... describes schematic information To use it, everything uses entity. Everything uses the netist portion of architectrue. Only the simulator uses the behavioral part. Only the layout program uses the layout section. Etc. A simple filter could strip parts not needed. This filter is so simple you could write it in "sed". It would be a one-liner in "awk". The big gain of this is that the whole family of tools can use the same files. No corporate tool set can make this claim.
