----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/748/ -----------------------------------------------------------
(Updated 2011-06-20 19:54:34.323028) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Changes ------- o. Delete the unused code instead of commenting out it; o. Remove the "#if ISA_HAS_DELAY_SLOT" because the isCondDelaySlot() is only used/set by MIPS ISA; o. Define readMiscRegNoEffect/setMiscRegNoEffect in inorder_dyn_inst.cc. Or else if we use this two functions in arch/mips/locked_mem.hh, ld will complain. (Sometimes, linked load instructions will make a thread halt then restart it. After that, the tick becomes a large number and it says 'because simulate() limit reached'. I haven't found the root cause yet. All I can do is using read/setMiscRegNoEffect instead of read/setMiscReg in arch/mips/locked_mem.hh...) Summary ------- Make the newly gem5 support mips branch likely instruction again. Fix 4 files: src/arch/mips/isa/formats/branch.isa src/cpu/inorder/inorder_dyn_inst.cc src/cpu/inorder/resources/branch_predictor.cc src/cpu/inorder/resources/fetch_seq_unit.cc Diffs (updated) ----- src/arch/mips/isa/formats/branch.isa f980df284118 src/cpu/inorder/inorder_dyn_inst.cc f980df284118 src/cpu/inorder/resources/branch_predictor.cc f980df284118 src/cpu/inorder/resources/fetch_seq_unit.cc f980df284118 Diff: http://reviews.m5sim.org/r/748/diff Testing ------- Tested. Thanks, Deyuan _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
