> On 2011-10-30 18:24:50, Nilay Vaish wrote: > > I think the definitions of IO instructions should change. Since IO > > instructions > > also act as memory barriers, the ld and st microops should be replaced with > > ldstl > > and stul.
No, they shouldn't. If those instructions need to be memory barriers, they need to be memory barriers on their own. The locking microops have to be in load/store pairs which these are not. Also the load microop will fault if a store would fault which is also not the desired behavior. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/897/#review1625 ----------------------------------------------------------- On 2011-10-30 18:22:08, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/897/ > ----------------------------------------------------------- > > (Updated 2011-10-30 18:22:08) > > > Review request for Default. > > > Summary > ------- > > X86 ISA: Change definitions of locked instructions > This patch is for changing the defintion of locked instructions. These > should behave as memory barriers and should be executed in a non speculative > fashion. > > > Diffs > ----- > > src/arch/x86/isa/insts/general_purpose/input_output/general_io.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/input_output/string_io.py > dd77c8d0a93e > src/arch/x86/isa/microops/ldstop.isa dd77c8d0a93e > > Diff: http://reviews.m5sim.org/r/897/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
