> On 2011-10-31 16:51:40, Gabe Black wrote: > > I'm not super excited about the duplicated code, but it's not totally > > unnecessary and I don't want to be too much of an obstacle to you fixing > > your bug. Be sure to run the regressions and look at the output carefully, > > and then I'm ok with this (and follow up with regression stat updates, as > > necessary). If it bugs me too much I'll go back and see if things can be > > refactored a bit.
Gabe, given the discussion that we had about the o3 cpu, it seems to me that this patch does not need to be committed. Instead I am posting a new patch for fence microop in x86. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/897/#review1630 ----------------------------------------------------------- On 2011-10-31 09:51:43, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/897/ > ----------------------------------------------------------- > > (Updated 2011-10-31 09:51:43) > > > Review request for Default. > > > Summary > ------- > > X86 ISA: Change definitions of locked instructions > This patch is for changing the defintion of locked instructions. These > should behave as memory barriers and should be executed in a non speculative > fashion. > > > Diffs > ----- > > src/arch/x86/isa/insts/general_purpose/input_output/general_io.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/input_output/string_io.py > dd77c8d0a93e > src/arch/x86/isa/microops/ldstop.isa dd77c8d0a93e > > Diff: http://reviews.m5sim.org/r/897/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
