> On 2011-10-30 22:51:20, Gabe Black wrote: > > You shouldn't change any of the places where ldstl or stul are used. They > > should have the properties they need implicitly, and regular loads/stores > > should take a parameter to set those optionally.
You could make the default for nonSpec and memBar True for ldstl or stul and False for the other loads and stores. Then it would make sense to still take an override for that parameter as an argument, but the default would be the right thing to do almost all of the time and no macroop definitions would need to change. The problem is that forcing those properties to be specified the same way every time the microop is used is redundant, verbose, and cumbersome, and those are exactly the things that having the microcode assembler is supposed to fix. Be careful how you implement that, though, since I suspect some of the subtleties of python may cause trouble. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/897/#review1628 ----------------------------------------------------------- On 2011-10-30 22:26:03, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/897/ > ----------------------------------------------------------- > > (Updated 2011-10-30 22:26:03) > > > Review request for Default. > > > Summary > ------- > > X86 ISA: Change definitions of locked instructions > This patch is for changing the defintion of locked instructions. These > should behave as memory barriers and should be executed in a non speculative > fashion. > > > Diffs > ----- > > src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py > dd77c8d0a93e > > src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/input_output/general_io.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/input_output/string_io.py > dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/logical.py dd77c8d0a93e > src/arch/x86/isa/insts/general_purpose/semaphores.py dd77c8d0a93e > src/arch/x86/isa/microops/ldstop.isa dd77c8d0a93e > > Diff: http://reviews.m5sim.org/r/897/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
