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I have added a trait hasTSO with each of the ISA. This is set to true only for x86 and false for the rest. - Nilay On 2011-11-18 15:35:05, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/908/ > ----------------------------------------------------------- > > (Updated 2011-11-18 15:35:05) > > > Review request for Default. > > > Summary > ------- > > O3 LSQ: Implement TSO > This patch makes O3's LSQ maintain total order between stores. Essentially > only the store at the head of the store buffer is allowed to be in flight. > Only after that store completes, the next store is issued to the memory > system. > > > Diffs > ----- > > src/arch/alpha/isa_traits.hh 330f8109b199 > src/arch/arm/isa_traits.hh 330f8109b199 > src/arch/mips/isa_traits.hh 330f8109b199 > src/arch/power/isa_traits.hh 330f8109b199 > src/arch/sparc/isa_traits.hh 330f8109b199 > src/arch/x86/isa_traits.hh 330f8109b199 > src/cpu/o3/lsq_unit.hh 330f8109b199 > src/cpu/o3/lsq_unit_impl.hh 330f8109b199 > > Diff: http://reviews.m5sim.org/r/908/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
