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src/mem/bus.cc <http://reviews.gem5.org/r/910/#comment2485> This should no longer be needed with the changes done to the functionalAccess in the cache now being able to respect forwardSnoops. src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/910/#comment2486> This should not be needed surely? If it should not forward snoops then don't forward it? src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/910/#comment2487> I don't understand why these changes are here. They make me even more confused about what an express snoop is and what it is not. What problem is this aiming to solve? src/mem/packet.hh <http://reviews.gem5.org/r/910/#comment2488> A packet should never be an express snoop and at any point loose that state (at least it messes with my brain and the ability to reason about what type of packets go where). - Andreas Hansson On Jan. 23, 2012, 10:14 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/910/ > ----------------------------------------------------------- > > (Updated Jan. 23, 2012, 10:14 a.m.) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Description > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > src/cpu/SConscript a1d5a0e2e970 > src/cpu/base.cc a1d5a0e2e970 > src/cpu/CheckerCPU.py a1d5a0e2e970 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/BaseCPU.py a1d5a0e2e970 > src/arch/arm/utility.cc a1d5a0e2e970 > src/arch/arm/tlb.hh a1d5a0e2e970 > src/arch/arm/tlb.cc a1d5a0e2e970 > src/arch/arm/isa/insts/misc.isa a1d5a0e2e970 > src/arch/arm/table_walker.hh a1d5a0e2e970 > src/arch/arm/table_walker.cc a1d5a0e2e970 > src/arch/arm/isa/insts/m5ops.isa a1d5a0e2e970 > src/arch/arm/isa.cc a1d5a0e2e970 > src/cpu/base_dyn_inst.hh a1d5a0e2e970 > src/cpu/base_dyn_inst_impl.hh a1d5a0e2e970 > src/cpu/checker/cpu.hh a1d5a0e2e970 > src/cpu/checker/cpu.cc a1d5a0e2e970 > src/cpu/checker/cpu_impl.hh a1d5a0e2e970 > src/cpu/checker/thread_context.hh a1d5a0e2e970 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py a1d5a0e2e970 > src/cpu/o3/O3Checker.py a1d5a0e2e970 > src/cpu/o3/checker_builder.cc a1d5a0e2e970 > src/cpu/o3/commit_impl.hh a1d5a0e2e970 > src/cpu/o3/cpu.hh a1d5a0e2e970 > src/cpu/o3/cpu.cc a1d5a0e2e970 > src/cpu/o3/dyn_inst_impl.hh a1d5a0e2e970 > src/cpu/o3/fetch_impl.hh a1d5a0e2e970 > src/cpu/o3/iew_impl.hh a1d5a0e2e970 > src/cpu/o3/lsq_unit_impl.hh a1d5a0e2e970 > src/cpu/o3/thread_context.hh a1d5a0e2e970 > src/cpu/o3/thread_context_impl.hh a1d5a0e2e970 > src/cpu/simple/BaseSimpleCPU.py a1d5a0e2e970 > src/cpu/simple/base.hh a1d5a0e2e970 > src/cpu/simple/base.cc a1d5a0e2e970 > src/cpu/simple_thread.hh a1d5a0e2e970 > src/cpu/thread_context.hh a1d5a0e2e970 > src/mem/bus.cc a1d5a0e2e970 > src/mem/cache/cache_impl.hh a1d5a0e2e970 > src/mem/packet.hh a1d5a0e2e970 > > Diff: http://reviews.gem5.org/r/910/diff/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
