> On Jan. 24, 2012, 12:41 a.m., Andreas Hansson wrote: > > src/mem/cache/cache_impl.hh, line 814 > > <http://reviews.gem5.org/r/910/diff/5/?file=21407#file21407line814> > > > > This should not be needed surely? If it should not forward snoops then > > don't forward it?
Also needed here because the functionalAccess() routine has no knowledge of which port the packet came in on, so this ensures forwardSnoops is respected (requests coming upstream) but also keeps regular accesses (downstream requests) working. > On Jan. 24, 2012, 12:41 a.m., Andreas Hansson wrote: > > src/mem/cache/cache_impl.hh, line 1675 > > <http://reviews.gem5.org/r/910/diff/5/?file=21407#file21407line1675> > > > > I don't understand why these changes are here. They make me even more > > confused about what an express snoop is and what it is not. What problem is > > this aiming to solve? This was a design decision on my part. For the timing path, when a request comes in the MemSidePort, handleSnoop() is called which then creates a new packet with expressSnoop set. Instead of adding more code with a functionalSnoop() routine and creating additional packets like the timing path, I allow the packet to set/unset itself as a snoop when it comes up the MemSidePort to re-use the functionalAccess() code. > On Jan. 24, 2012, 12:41 a.m., Andreas Hansson wrote: > > src/mem/bus.cc, line 482 > > <http://reviews.gem5.org/r/910/diff/5/?file=21406#file21406line482> > > > > This should no longer be needed with the changes done to the > > functionalAccess in the cache now being able to respect forwardSnoops. This is needed in the case there is a coherent device that can be snooped on the bus (cache has forwardSnoops=true). The bus needs to identify if the packet is a forwarded snoop to prevent it from sending it erroneously to a destination port. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/910/#review1986 ----------------------------------------------------------- On Jan. 23, 2012, 10:14 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/910/ > ----------------------------------------------------------- > > (Updated Jan. 23, 2012, 10:14 a.m.) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Description > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > src/cpu/SConscript a1d5a0e2e970 > src/cpu/base.cc a1d5a0e2e970 > src/cpu/CheckerCPU.py a1d5a0e2e970 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/BaseCPU.py a1d5a0e2e970 > src/arch/arm/utility.cc a1d5a0e2e970 > src/arch/arm/tlb.hh a1d5a0e2e970 > src/arch/arm/tlb.cc a1d5a0e2e970 > src/arch/arm/isa/insts/misc.isa a1d5a0e2e970 > src/arch/arm/table_walker.hh a1d5a0e2e970 > src/arch/arm/table_walker.cc a1d5a0e2e970 > src/arch/arm/isa/insts/m5ops.isa a1d5a0e2e970 > src/arch/arm/isa.cc a1d5a0e2e970 > src/cpu/base_dyn_inst.hh a1d5a0e2e970 > src/cpu/base_dyn_inst_impl.hh a1d5a0e2e970 > src/cpu/checker/cpu.hh a1d5a0e2e970 > src/cpu/checker/cpu.cc a1d5a0e2e970 > src/cpu/checker/cpu_impl.hh a1d5a0e2e970 > src/cpu/checker/thread_context.hh a1d5a0e2e970 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py a1d5a0e2e970 > src/cpu/o3/O3Checker.py a1d5a0e2e970 > src/cpu/o3/checker_builder.cc a1d5a0e2e970 > src/cpu/o3/commit_impl.hh a1d5a0e2e970 > src/cpu/o3/cpu.hh a1d5a0e2e970 > src/cpu/o3/cpu.cc a1d5a0e2e970 > src/cpu/o3/dyn_inst_impl.hh a1d5a0e2e970 > src/cpu/o3/fetch_impl.hh a1d5a0e2e970 > src/cpu/o3/iew_impl.hh a1d5a0e2e970 > src/cpu/o3/lsq_unit_impl.hh a1d5a0e2e970 > src/cpu/o3/thread_context.hh a1d5a0e2e970 > src/cpu/o3/thread_context_impl.hh a1d5a0e2e970 > src/cpu/simple/BaseSimpleCPU.py a1d5a0e2e970 > src/cpu/simple/base.hh a1d5a0e2e970 > src/cpu/simple/base.cc a1d5a0e2e970 > src/cpu/simple_thread.hh a1d5a0e2e970 > src/cpu/thread_context.hh a1d5a0e2e970 > src/mem/bus.cc a1d5a0e2e970 > src/mem/cache/cache_impl.hh a1d5a0e2e970 > src/mem/packet.hh a1d5a0e2e970 > > Diff: http://reviews.gem5.org/r/910/diff/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
