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src/cpu/simple_thread.cc <http://reviews.m5sim.org/r/943/#comment2337> I also believe the SimpleThread should have nothing to do with deleting the port proxies. I have moved this to the ThreadState destructor since that class is responsible for the creation of the proxies. - Andreas On 2011-12-23 00:58:45, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/943/ > ----------------------------------------------------------- > > (Updated 2011-12-23 00:58:45) > > > Review request for Default. > > > Summary > ------- > > MEM: Add port proxies instead of non-structural ports > > This is a complete re-make of the previous patches taking all the > feedback into account. > > Port proxies are used to replace non-structural ports, and thus enable > all ports in the system to correspond to a structural entity. This has > the advantage of accessing memory through the normal memory subsystem > and thus allowing any constellation of distributed memories, address > maps, etc. Most accesses are done through the "system port" that is > used for loading binaries, debugging etc. For the entities that belong > to the CPU, e.g. threads and thread contexts, they wrap the CPU data > port in a port proxy. > > The following replacements are made: > FunctionalPort > PortProxy > TranslatingPort > SETranslatingPortProxy > VirtualPort > FSTranslatingPortProxy > > > Diffs > ----- > > configs/common/FSConfig.py ca98021c3f96 > configs/ruby/Ruby.py ca98021c3f96 > src/arch/alpha/freebsd/system.cc ca98021c3f96 > src/arch/alpha/linux/process.cc ca98021c3f96 > src/arch/alpha/linux/system.hh ca98021c3f96 > src/arch/alpha/linux/system.cc ca98021c3f96 > src/arch/alpha/linux/threadinfo.hh ca98021c3f96 > src/arch/alpha/remote_gdb.cc ca98021c3f96 > src/arch/alpha/stacktrace.cc ca98021c3f96 > src/arch/alpha/system.hh ca98021c3f96 > src/arch/alpha/system.cc ca98021c3f96 > src/arch/alpha/tru64/process.cc ca98021c3f96 > src/arch/alpha/tru64/system.cc ca98021c3f96 > src/arch/alpha/utility.cc ca98021c3f96 > src/arch/alpha/vtophys.hh ca98021c3f96 > src/arch/alpha/vtophys.cc ca98021c3f96 > src/arch/arm/linux/process.cc ca98021c3f96 > src/arch/arm/linux/system.cc ca98021c3f96 > src/arch/arm/process.cc ca98021c3f96 > src/arch/arm/stacktrace.cc ca98021c3f96 > src/arch/arm/system.hh ca98021c3f96 > src/arch/arm/system.cc ca98021c3f96 > src/arch/arm/utility.cc ca98021c3f96 > src/arch/arm/vtophys.cc ca98021c3f96 > src/arch/mips/linux/process.cc ca98021c3f96 > src/arch/mips/linux/system.cc ca98021c3f96 > src/arch/mips/linux/threadinfo.hh ca98021c3f96 > src/arch/mips/stacktrace.cc ca98021c3f96 > src/arch/mips/utility.cc ca98021c3f96 > src/arch/power/linux/process.cc ca98021c3f96 > src/arch/power/process.cc ca98021c3f96 > src/arch/sparc/linux/syscalls.cc ca98021c3f96 > src/arch/sparc/process.cc ca98021c3f96 > src/arch/sparc/solaris/process.cc ca98021c3f96 > src/arch/sparc/system.hh ca98021c3f96 > src/arch/sparc/system.cc ca98021c3f96 > src/arch/sparc/utility.cc ca98021c3f96 > src/arch/sparc/vtophys.cc ca98021c3f96 > src/arch/x86/bios/intelmp.hh ca98021c3f96 > src/arch/x86/bios/intelmp.cc ca98021c3f96 > src/arch/x86/bios/smbios.hh ca98021c3f96 > src/arch/x86/bios/smbios.cc ca98021c3f96 > src/arch/x86/linux/syscalls.cc ca98021c3f96 > src/arch/x86/linux/system.cc ca98021c3f96 > src/arch/x86/process.cc ca98021c3f96 > src/arch/x86/stacktrace.cc ca98021c3f96 > src/arch/x86/system.cc ca98021c3f96 > src/base/loader/elf_object.hh ca98021c3f96 > src/base/loader/elf_object.cc ca98021c3f96 > src/base/loader/hex_file.hh ca98021c3f96 > src/base/loader/hex_file.cc ca98021c3f96 > src/base/loader/object_file.hh ca98021c3f96 > src/base/loader/object_file.cc ca98021c3f96 > src/base/remote_gdb.cc ca98021c3f96 > src/cpu/checker/thread_context.hh ca98021c3f96 > src/cpu/inorder/cpu.cc ca98021c3f96 > src/cpu/inorder/thread_context.hh ca98021c3f96 > src/cpu/inorder/thread_context.cc ca98021c3f96 > src/cpu/o3/thread_context.hh ca98021c3f96 > src/cpu/o3/thread_context_impl.hh ca98021c3f96 > src/cpu/ozone/cpu.hh ca98021c3f96 > src/cpu/ozone/cpu_impl.hh ca98021c3f96 > src/cpu/simple_thread.hh ca98021c3f96 > src/cpu/simple_thread.cc ca98021c3f96 > src/cpu/thread_context.hh ca98021c3f96 > src/cpu/thread_state.hh ca98021c3f96 > src/cpu/thread_state.cc ca98021c3f96 > src/dev/simple_disk.cc ca98021c3f96 > src/kern/tru64/tru64.hh ca98021c3f96 > src/kern/tru64/tru64_events.cc ca98021c3f96 > src/mem/SConscript ca98021c3f96 > src/mem/bus.cc ca98021c3f96 > src/mem/fs_translating_port_proxy.hh PRE-CREATION > src/mem/fs_translating_port_proxy.cc PRE-CREATION > src/mem/port.hh ca98021c3f96 > src/mem/port_proxy.hh PRE-CREATION > src/mem/port_proxy.cc PRE-CREATION > src/mem/ruby/system/RubyPort.cc ca98021c3f96 > src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION > src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION > src/mem/ruby/system/SConscript ca98021c3f96 > src/mem/ruby/system/Sequencer.py ca98021c3f96 > src/mem/se_translating_port_proxy.hh PRE-CREATION > src/mem/se_translating_port_proxy.cc PRE-CREATION > src/mem/translating_port.hh ca98021c3f96 > src/mem/translating_port.cc ca98021c3f96 > src/mem/vport.hh ca98021c3f96 > src/mem/vport.cc ca98021c3f96 > src/sim/arguments.hh ca98021c3f96 > src/sim/process.hh ca98021c3f96 > src/sim/process.cc ca98021c3f96 > src/sim/process_impl.hh ca98021c3f96 > src/sim/syscall_emul.hh ca98021c3f96 > src/sim/syscall_emul.cc ca98021c3f96 > src/sim/system.hh ca98021c3f96 > src/sim/system.cc ca98021c3f96 > src/sim/vptr.hh ca98021c3f96 > tests/configs/inorder-timing.py ca98021c3f96 > tests/configs/memtest.py ca98021c3f96 > tests/configs/o3-timing-mp.py ca98021c3f96 > tests/configs/o3-timing.py ca98021c3f96 > tests/configs/simple-atomic-mp.py ca98021c3f96 > tests/configs/simple-atomic.py ca98021c3f96 > tests/configs/simple-timing-mp-ruby.py ca98021c3f96 > tests/configs/simple-timing-mp.py ca98021c3f96 > tests/configs/simple-timing-ruby.py ca98021c3f96 > tests/configs/simple-timing.py ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/943/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
