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(Updated 2012-01-10 09:20:54.998430) Review request for Default. Summary ------- MEM: Add port proxies instead of non-structural ports Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy Diffs (updated) ----- configs/common/FSConfig.py a1d5a0e2e970 configs/example/se.py a1d5a0e2e970 configs/ruby/Ruby.py a1d5a0e2e970 src/arch/alpha/freebsd/system.cc a1d5a0e2e970 src/arch/alpha/linux/process.cc a1d5a0e2e970 src/arch/alpha/linux/system.hh a1d5a0e2e970 src/arch/alpha/linux/system.cc a1d5a0e2e970 src/arch/alpha/linux/threadinfo.hh a1d5a0e2e970 src/arch/alpha/remote_gdb.cc a1d5a0e2e970 src/arch/alpha/stacktrace.cc a1d5a0e2e970 src/arch/alpha/system.hh a1d5a0e2e970 src/arch/alpha/system.cc a1d5a0e2e970 src/arch/alpha/tru64/process.cc a1d5a0e2e970 src/arch/alpha/tru64/system.cc a1d5a0e2e970 src/arch/alpha/utility.cc a1d5a0e2e970 src/arch/alpha/vtophys.hh a1d5a0e2e970 src/arch/alpha/vtophys.cc a1d5a0e2e970 src/arch/arm/linux/process.cc a1d5a0e2e970 src/arch/arm/linux/system.cc a1d5a0e2e970 src/arch/arm/process.cc a1d5a0e2e970 src/arch/arm/stacktrace.cc a1d5a0e2e970 src/arch/arm/system.hh a1d5a0e2e970 src/arch/arm/system.cc a1d5a0e2e970 src/arch/arm/utility.cc a1d5a0e2e970 src/arch/arm/vtophys.cc a1d5a0e2e970 src/arch/mips/linux/process.cc a1d5a0e2e970 src/arch/mips/linux/system.cc a1d5a0e2e970 src/arch/mips/linux/threadinfo.hh a1d5a0e2e970 src/arch/mips/stacktrace.cc a1d5a0e2e970 src/arch/mips/utility.cc a1d5a0e2e970 src/arch/power/linux/process.cc a1d5a0e2e970 src/arch/power/process.cc a1d5a0e2e970 src/arch/sparc/linux/syscalls.cc a1d5a0e2e970 src/arch/sparc/process.cc a1d5a0e2e970 src/arch/sparc/solaris/process.cc a1d5a0e2e970 src/arch/sparc/system.hh a1d5a0e2e970 src/arch/sparc/system.cc a1d5a0e2e970 src/arch/sparc/utility.cc a1d5a0e2e970 src/arch/sparc/vtophys.cc a1d5a0e2e970 src/arch/x86/bios/intelmp.hh a1d5a0e2e970 src/arch/x86/bios/intelmp.cc a1d5a0e2e970 src/arch/x86/bios/smbios.hh a1d5a0e2e970 src/arch/x86/bios/smbios.cc a1d5a0e2e970 src/arch/x86/linux/syscalls.cc a1d5a0e2e970 src/arch/x86/linux/system.cc a1d5a0e2e970 src/arch/x86/process.cc a1d5a0e2e970 src/arch/x86/stacktrace.cc a1d5a0e2e970 src/arch/x86/system.cc a1d5a0e2e970 src/base/loader/elf_object.hh a1d5a0e2e970 src/base/loader/elf_object.cc a1d5a0e2e970 src/base/loader/hex_file.hh a1d5a0e2e970 src/base/loader/hex_file.cc a1d5a0e2e970 src/base/loader/object_file.hh a1d5a0e2e970 src/base/loader/object_file.cc a1d5a0e2e970 src/base/remote_gdb.cc a1d5a0e2e970 src/cpu/checker/thread_context.hh a1d5a0e2e970 src/cpu/inorder/cpu.hh a1d5a0e2e970 src/cpu/inorder/cpu.cc a1d5a0e2e970 src/cpu/inorder/resources/cache_unit.hh a1d5a0e2e970 src/cpu/inorder/resources/cache_unit.cc a1d5a0e2e970 src/cpu/inorder/thread_context.hh a1d5a0e2e970 src/cpu/inorder/thread_context.cc a1d5a0e2e970 src/cpu/o3/cpu.hh a1d5a0e2e970 src/cpu/o3/cpu.cc a1d5a0e2e970 src/cpu/o3/lsq.hh a1d5a0e2e970 src/cpu/o3/lsq_impl.hh a1d5a0e2e970 src/cpu/o3/thread_context.hh a1d5a0e2e970 src/cpu/o3/thread_context_impl.hh a1d5a0e2e970 src/cpu/ozone/cpu.hh a1d5a0e2e970 src/cpu/ozone/cpu_impl.hh a1d5a0e2e970 src/cpu/simple/atomic.hh a1d5a0e2e970 src/cpu/simple/atomic.cc a1d5a0e2e970 src/cpu/simple/timing.hh a1d5a0e2e970 src/cpu/simple/timing.cc a1d5a0e2e970 src/cpu/simple_thread.hh a1d5a0e2e970 src/cpu/simple_thread.cc a1d5a0e2e970 src/cpu/thread_context.hh a1d5a0e2e970 src/cpu/thread_state.hh a1d5a0e2e970 src/cpu/thread_state.cc a1d5a0e2e970 src/dev/simple_disk.cc a1d5a0e2e970 src/kern/tru64/tru64.hh a1d5a0e2e970 src/kern/tru64/tru64_events.cc a1d5a0e2e970 src/mem/SConscript a1d5a0e2e970 src/mem/fs_translating_port_proxy.hh PRE-CREATION src/mem/fs_translating_port_proxy.cc PRE-CREATION src/mem/port.hh a1d5a0e2e970 src/mem/port_proxy.hh PRE-CREATION src/mem/port_proxy.cc PRE-CREATION src/mem/ruby/system/RubyPort.cc a1d5a0e2e970 src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION src/mem/ruby/system/SConscript a1d5a0e2e970 src/mem/ruby/system/Sequencer.py a1d5a0e2e970 src/mem/se_translating_port_proxy.hh PRE-CREATION src/mem/se_translating_port_proxy.cc PRE-CREATION src/mem/translating_port.hh a1d5a0e2e970 src/mem/translating_port.cc a1d5a0e2e970 src/mem/vport.hh a1d5a0e2e970 src/mem/vport.cc a1d5a0e2e970 src/sim/arguments.hh a1d5a0e2e970 src/sim/process.hh a1d5a0e2e970 src/sim/process.cc a1d5a0e2e970 src/sim/process_impl.hh a1d5a0e2e970 src/sim/syscall_emul.hh a1d5a0e2e970 src/sim/syscall_emul.cc a1d5a0e2e970 src/sim/system.hh a1d5a0e2e970 src/sim/system.cc a1d5a0e2e970 src/sim/vptr.hh a1d5a0e2e970 tests/configs/inorder-timing.py a1d5a0e2e970 tests/configs/memtest.py a1d5a0e2e970 tests/configs/o3-timing-mp.py a1d5a0e2e970 tests/configs/o3-timing.py a1d5a0e2e970 tests/configs/simple-atomic-mp.py a1d5a0e2e970 tests/configs/simple-atomic.py a1d5a0e2e970 tests/configs/simple-timing-mp-ruby.py a1d5a0e2e970 tests/configs/simple-timing-mp.py a1d5a0e2e970 tests/configs/simple-timing-ruby.py a1d5a0e2e970 tests/configs/simple-timing.py a1d5a0e2e970 Diff: http://reviews.m5sim.org/r/943/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
