> On 2012-01-11 20:35:11, Steve Reinhardt wrote: > > Looks pretty good... several comments below (some minor, a couple more > > significant ones), and there's also the pointer declaration style issue to > > iron out, but it looks pretty close. > > > > I think this is my last patch to review of your series, Andreas. I think > > there were only a couple (including this one) I didn't mark as "ship it"... > > those are the only ones I care to see again before you commit. > > > > Thanks for all your hard work! > > Andreas Hansson wrote: > Thanks for the review. > > Here are a few lines from the patch file, and I have no idea why the > board does not like the rename: > > diff --git a/src/mem/vport.cc b/src/mem/fs_translating_port_proxy.cc > rename from src/mem/vport.cc > rename to src/mem/fs_translating_port_proxy.cc > --- a/src/mem/vport.cc > +++ b/src/mem/fs_translating_port_proxy.cc
I would suggest to adopt this patch as it is and leave the tidying up for a separate patch. This minimises the changes, even if the reviewboard does not seem to understand the renaming. If we take this approach, is there anything you still want to see changed? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/943/#review1921 ----------------------------------------------------------- On 2012-01-12 10:19:12, Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/943/ > ----------------------------------------------------------- > > (Updated 2012-01-12 10:19:12) > > > Review request for Default. > > > Summary > ------- > > MEM: Add port proxies instead of non-structural ports > > Port proxies are used to replace non-structural ports, and thus enable > all ports in the system to correspond to a structural entity. This has > the advantage of accessing memory through the normal memory subsystem > and thus allowing any constellation of distributed memories, address > maps, etc. Most accesses are done through the "system port" that is > used for loading binaries, debugging etc. For the entities that belong > to the CPU, e.g. threads and thread contexts, they wrap the CPU data > port in a port proxy. > > The following replacements are made: > FunctionalPort > PortProxy > TranslatingPort > SETranslatingPortProxy > VirtualPort > FSTranslatingPortProxy > > > Diffs > ----- > > configs/common/FSConfig.py 99ba36eaa789 > configs/example/se.py 99ba36eaa789 > configs/ruby/Ruby.py 99ba36eaa789 > src/arch/alpha/freebsd/system.cc 99ba36eaa789 > src/arch/alpha/linux/process.cc 99ba36eaa789 > src/arch/alpha/linux/system.hh 99ba36eaa789 > src/arch/alpha/linux/system.cc 99ba36eaa789 > src/arch/alpha/linux/threadinfo.hh 99ba36eaa789 > src/arch/alpha/remote_gdb.cc 99ba36eaa789 > src/arch/alpha/stacktrace.cc 99ba36eaa789 > src/arch/alpha/system.hh 99ba36eaa789 > src/arch/alpha/system.cc 99ba36eaa789 > src/arch/alpha/tru64/process.cc 99ba36eaa789 > src/arch/alpha/tru64/system.cc 99ba36eaa789 > src/arch/alpha/utility.cc 99ba36eaa789 > src/arch/alpha/vtophys.hh 99ba36eaa789 > src/arch/alpha/vtophys.cc 99ba36eaa789 > src/arch/arm/linux/process.cc 99ba36eaa789 > src/arch/arm/linux/system.cc 99ba36eaa789 > src/arch/arm/process.cc 99ba36eaa789 > src/arch/arm/stacktrace.cc 99ba36eaa789 > src/arch/arm/system.hh 99ba36eaa789 > src/arch/arm/system.cc 99ba36eaa789 > src/arch/arm/utility.cc 99ba36eaa789 > src/arch/arm/vtophys.cc 99ba36eaa789 > src/arch/mips/linux/process.cc 99ba36eaa789 > src/arch/mips/linux/system.cc 99ba36eaa789 > src/arch/mips/linux/threadinfo.hh 99ba36eaa789 > src/arch/mips/stacktrace.cc 99ba36eaa789 > src/arch/mips/utility.cc 99ba36eaa789 > src/arch/power/linux/process.cc 99ba36eaa789 > src/arch/power/process.cc 99ba36eaa789 > src/arch/sparc/linux/syscalls.cc 99ba36eaa789 > src/arch/sparc/process.cc 99ba36eaa789 > src/arch/sparc/solaris/process.cc 99ba36eaa789 > src/arch/sparc/system.hh 99ba36eaa789 > src/arch/sparc/system.cc 99ba36eaa789 > src/arch/sparc/utility.cc 99ba36eaa789 > src/arch/sparc/vtophys.cc 99ba36eaa789 > src/arch/x86/bios/intelmp.hh 99ba36eaa789 > src/arch/x86/bios/intelmp.cc 99ba36eaa789 > src/arch/x86/bios/smbios.hh 99ba36eaa789 > src/arch/x86/bios/smbios.cc 99ba36eaa789 > src/arch/x86/linux/syscalls.cc 99ba36eaa789 > src/arch/x86/linux/system.cc 99ba36eaa789 > src/arch/x86/process.cc 99ba36eaa789 > src/arch/x86/stacktrace.cc 99ba36eaa789 > src/arch/x86/system.cc 99ba36eaa789 > src/base/loader/elf_object.hh 99ba36eaa789 > src/base/loader/elf_object.cc 99ba36eaa789 > src/base/loader/hex_file.hh 99ba36eaa789 > src/base/loader/hex_file.cc 99ba36eaa789 > src/base/loader/object_file.hh 99ba36eaa789 > src/base/loader/object_file.cc 99ba36eaa789 > src/base/remote_gdb.cc 99ba36eaa789 > src/cpu/checker/thread_context.hh 99ba36eaa789 > src/cpu/inorder/cpu.hh 99ba36eaa789 > src/cpu/inorder/cpu.cc 99ba36eaa789 > src/cpu/inorder/resources/cache_unit.hh 99ba36eaa789 > src/cpu/inorder/resources/cache_unit.cc 99ba36eaa789 > src/cpu/inorder/thread_context.hh 99ba36eaa789 > src/cpu/inorder/thread_context.cc 99ba36eaa789 > src/cpu/o3/cpu.hh 99ba36eaa789 > src/cpu/o3/cpu.cc 99ba36eaa789 > src/cpu/o3/lsq.hh 99ba36eaa789 > src/cpu/o3/lsq_impl.hh 99ba36eaa789 > src/cpu/o3/thread_context.hh 99ba36eaa789 > src/cpu/o3/thread_context_impl.hh 99ba36eaa789 > src/cpu/ozone/cpu.hh 99ba36eaa789 > src/cpu/ozone/cpu_impl.hh 99ba36eaa789 > src/cpu/simple/atomic.hh 99ba36eaa789 > src/cpu/simple/atomic.cc 99ba36eaa789 > src/cpu/simple/timing.hh 99ba36eaa789 > src/cpu/simple/timing.cc 99ba36eaa789 > src/cpu/simple_thread.hh 99ba36eaa789 > src/cpu/simple_thread.cc 99ba36eaa789 > src/cpu/thread_context.hh 99ba36eaa789 > src/cpu/thread_state.hh 99ba36eaa789 > src/cpu/thread_state.cc 99ba36eaa789 > src/dev/simple_disk.cc 99ba36eaa789 > src/kern/tru64/tru64.hh 99ba36eaa789 > src/kern/tru64/tru64_events.cc 99ba36eaa789 > src/mem/SConscript 99ba36eaa789 > src/mem/fs_translating_port_proxy.hh PRE-CREATION > src/mem/fs_translating_port_proxy.cc PRE-CREATION > src/mem/port.hh 99ba36eaa789 > src/mem/port_proxy.hh PRE-CREATION > src/mem/port_proxy.cc PRE-CREATION > src/mem/ruby/system/RubyPort.cc 99ba36eaa789 > src/mem/ruby/system/RubyPortProxy.hh PRE-CREATION > src/mem/ruby/system/RubyPortProxy.cc PRE-CREATION > src/mem/ruby/system/SConscript 99ba36eaa789 > src/mem/ruby/system/Sequencer.py 99ba36eaa789 > src/mem/se_translating_port_proxy.hh PRE-CREATION > src/mem/se_translating_port_proxy.cc PRE-CREATION > src/mem/translating_port.hh 99ba36eaa789 > src/mem/translating_port.cc 99ba36eaa789 > src/mem/vport.hh 99ba36eaa789 > src/mem/vport.cc 99ba36eaa789 > src/sim/arguments.hh 99ba36eaa789 > src/sim/process.hh 99ba36eaa789 > src/sim/process.cc 99ba36eaa789 > src/sim/process_impl.hh 99ba36eaa789 > src/sim/syscall_emul.hh 99ba36eaa789 > src/sim/syscall_emul.cc 99ba36eaa789 > src/sim/system.hh 99ba36eaa789 > src/sim/system.cc 99ba36eaa789 > src/sim/vptr.hh 99ba36eaa789 > tests/configs/inorder-timing.py 99ba36eaa789 > tests/configs/memtest-ruby.py 99ba36eaa789 > tests/configs/memtest.py 99ba36eaa789 > tests/configs/o3-timing-mp.py 99ba36eaa789 > tests/configs/o3-timing.py 99ba36eaa789 > tests/configs/rubytest-ruby.py 99ba36eaa789 > tests/configs/simple-atomic-mp.py 99ba36eaa789 > tests/configs/simple-atomic.py 99ba36eaa789 > tests/configs/simple-timing-mp-ruby.py 99ba36eaa789 > tests/configs/simple-timing-mp.py 99ba36eaa789 > tests/configs/simple-timing-ruby.py 99ba36eaa789 > tests/configs/simple-timing.py 99ba36eaa789 > > Diff: http://reviews.m5sim.org/r/943/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
