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Looks good... thanks, Nilay. src/cpu/o3/O3CPU.py <http://reviews.m5sim.org/r/908/#comment2449> Seems like we should do something like: needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', "Memory model") - Steve On 2012-01-13 04:57:18, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/908/ > ----------------------------------------------------------- > > (Updated 2012-01-13 04:57:18) > > > Review request for Default. > > > Summary > ------- > > Changeset 8702:9a5651e7bd5b > --------------------------- > O3 LSQ: Implement TSO > This patch makes O3's LSQ maintain total order between stores. Essentially > only the store at the head of the store buffer is allowed to be in flight. > Only after that store completes, the next store is issued to the memory > system. > > > Diffs > ----- > > src/cpu/o3/O3CPU.py f348cf78072c > src/cpu/o3/cpu.hh f348cf78072c > src/cpu/o3/cpu.cc f348cf78072c > src/cpu/o3/lsq_unit.hh f348cf78072c > src/cpu/o3/lsq_unit_impl.hh f348cf78072c > > Diff: http://reviews.m5sim.org/r/908/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
