----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/908/ -----------------------------------------------------------
(Updated 2012-01-10 16:22:46.269309) Review request for Default. Summary ------- O3 LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. Diffs (updated) ----- src/cpu/o3/O3CPU.py d0ce111b34ef src/cpu/o3/cpu.hh d0ce111b34ef src/cpu/o3/cpu.cc d0ce111b34ef src/cpu/o3/lsq_unit.hh d0ce111b34ef src/cpu/o3/lsq_unit_impl.hh d0ce111b34ef Diff: http://reviews.m5sim.org/r/908/diff Testing ------- Thanks, Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
