> On April 21, 2012, 8:18 p.m., Gabe Black wrote: > > It shouldn't be necessary to specify two different sets of flags. The > > microops already either read the flags, or write the flags with an implicit > > read to support partial updating, but they don't ever do both (please tell > > me if I'm forgetting one that does). In either of those cases, we can > > automatically figure out what goes in a read set or a write set. If it's a > > microop that reads flags (conditional, in other words) then the flags are > > all reads. If it's a microop that writes flags (an add, subtract, etc.) > > then it writes, and reads anything that isn't completely covered by writes.
There are some instructions that do both. For example Adc reads the carry bit and then updates the flag bits. I think there a couple more that read some flag bit and writes the EZFbit. > On April 21, 2012, 8:18 p.m., Gabe Black wrote: > > src/arch/x86/isa/microops/regop.isa, line 437 > > <http://reviews.gem5.org/r/1161/diff/1/?file=26114#file26114line437> > > > > Why did you make a copy of this class? The design that I have in mind, will not have the original class finally. Essentially the copy will not exist. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1161/#review2572 ----------------------------------------------------------- On April 21, 2012, 1:29 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1161/ > ----------------------------------------------------------- > > (Updated April 21, 2012, 1:29 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8963:d6f5887beaf0 > --------------------------- > X86: Break flags in to read and write sets > Currently, each instruction specifies the flags it is going to read, write > as a single set. This patch introduces separate read and write sets. This > is required for reducing the RAW dependencies. If no flag bit needs to be > read (empty read set), and all the flag bits are being written, then there > is no need to read the flagbits register. The dependencies will be reduced > further when the ccflagbits register is split into multiple registers. > > > Diffs > ----- > > src/arch/x86/isa/microops/fpop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/regop.isa 0bba1c59b4d1 > > Diff: http://reviews.gem5.org/r/1161/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
