I'd like to make a meta-comment here. It's good to communicate what
you're doing so you don't get a long ways in and find out you went the
wrong way, but at the same time it's important to know that what
you've got is actually going to work before you go to get it checked
in. With what I'm expecting will be a significant change like this, I
think it's best to have some good discussion about how your design
will work, then to implement it and get it working, and then to get it
checked in in reviewable pieces. If you get all the way to something
that works, you'll be able to see what changes you made that were
ultimately unnecessary, what things you overlooked that forced
something to be done a different way, etc. What you've got here I
don't think will work and does things it doesn't need to do. It's in
roughly the right direction though, so if you took it the rest of the
way I think those problems would get fixed.
Gabe
Quoting Nilay Vaish <[email protected]>:
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1161/
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Review request for Default.
Description
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Changeset 8963:d6f5887beaf0
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X86: Break flags in to read and write sets
Currently, each instruction specifies the flags it is going to read, write
as a single set. This patch introduces separate read and write sets. This
is required for reducing the RAW dependencies. If no flag bit needs to be
read (empty read set), and all the flag bits are being written, then there
is no need to read the flagbits register. The dependencies will be reduced
further when the ccflagbits register is split into multiple registers.
Diffs
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src/arch/x86/isa/microops/fpop.isa 0bba1c59b4d1
src/arch/x86/isa/microops/regop.isa 0bba1c59b4d1
Diff: http://reviews.gem5.org/r/1161/diff/
Testing
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Thanks,
Nilay Vaish
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