> On April 21, 2012, 8:18 p.m., Gabe Black wrote: > > src/arch/x86/isa/microops/regop.isa, line 437 > > <http://reviews.gem5.org/r/1161/diff/1/?file=26114#file26114line437> > > > > Why did you make a copy of this class? > > Nilay Vaish wrote: > The design that I have in mind, will not have the original class > finally. Essentially the copy will not exist.
Lets avoid this step in the middle then. It makes it harder to see what's different, and there's all the duplication in the mean time. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1161/#review2572 ----------------------------------------------------------- On April 21, 2012, 1:29 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1161/ > ----------------------------------------------------------- > > (Updated April 21, 2012, 1:29 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8963:d6f5887beaf0 > --------------------------- > X86: Break flags in to read and write sets > Currently, each instruction specifies the flags it is going to read, write > as a single set. This patch introduces separate read and write sets. This > is required for reducing the RAW dependencies. If no flag bit needs to be > read (empty read set), and all the flag bits are being written, then there > is no need to read the flagbits register. The dependencies will be reduced > further when the ccflagbits register is split into multiple registers. > > > Diffs > ----- > > src/arch/x86/isa/microops/fpop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/regop.isa 0bba1c59b4d1 > > Diff: http://reviews.gem5.org/r/1161/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
