> On April 22, 2012, 6:09 p.m., Steve Reinhardt wrote: > > src/arch/x86/isa/microops/regop.isa, line 372 > > <http://reviews.gem5.org/r/1161/diff/2/?file=26117#file26117line372> > > > > Could use some comments here on what this class is (same for RegOp3 and > > RegOp4). I realize that's not in keeping with the style of this file ;-). > > > > Also, totally outside the scope of this patch, but as a longer-term > > goal it would be nice to take these really big hunks of python and just put > > them in .py files and import them indirectly... > > > > Conversely, it would be nice if the microcode files that are .py files > > but which each exist solely to define a single really long string constant > > were redone as .isa files or something similar. > > > > Sorry for the big tangent, but this just reminded me of those thoughts.
I'll comment those classes. I don't get your metric for deciding between what should be in .isa files, and what goes into .py files. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1161/#review2590 ----------------------------------------------------------- On April 22, 2012, 8:32 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1161/ > ----------------------------------------------------------- > > (Updated April 22, 2012, 8:32 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8963:eb9b72c1c919 > --------------------------- > X86: Break flags in to read and write sets > Currently, each instruction specifies the flags it is going to read, write > as a single set. This patch introduces separate read and write sets. This > is required for reducing the RAW dependencies. If no flag bit needs to be > read (empty read set), and all the flag bits are being written, then there > is no need to read the flagbits register. The dependencies will be reduced > further when the ccflagbits register is split into multiple registers. > > > Diffs > ----- > > src/arch/x86/isa/microops/fpop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/regop.isa 0bba1c59b4d1 > > Diff: http://reviews.gem5.org/r/1161/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
