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(Updated May 16, 2012, 4:38 p.m.) Review request for Default. Description (updated) ------- Changeset 9013:8dcee4635013 --------------------------- X86: Split Condition Code register This patch moves the ECF and EZF bits to a separate register. This is just an example patch for discussion. This is how I am proposing we should split the register. If this is acceptable, then ultimately we will have the following registers -- [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Diffs (updated) ----- src/arch/x86/isa/microops/debug.isa eb9751c05748 src/arch/x86/isa/microops/fpop.isa eb9751c05748 src/arch/x86/isa/microops/regop.isa eb9751c05748 src/arch/x86/isa/microops/seqop.isa eb9751c05748 src/arch/x86/isa/microops/specop.isa eb9751c05748 src/arch/x86/isa/operands.isa eb9751c05748 src/arch/x86/x86_traits.hh eb9751c05748 Diff: http://reviews.gem5.org/r/1166/diff/ Testing ------- Boots Linux with atomic cpu. Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
