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(Updated May 18, 2012, 11:55 a.m.) Review request for Default. Description (updated) ------- Changeset 9008:44471dbd9f5c --------------------------- X86: Split Condition Code register This patch moves the ECF and EZF bits to the uccFlagBits and the CF and OF bits to cfofFlag registers. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Diffs (updated) ----- src/arch/x86/isa/microops/debug.isa 7100059f7bfd src/arch/x86/isa/microops/fpop.isa 7100059f7bfd src/arch/x86/isa/microops/mediaop.isa 7100059f7bfd src/arch/x86/isa/microops/regop.isa 7100059f7bfd src/arch/x86/isa/microops/seqop.isa 7100059f7bfd src/arch/x86/isa/microops/specop.isa 7100059f7bfd src/arch/x86/isa/operands.isa 7100059f7bfd src/arch/x86/regs/misc.hh 7100059f7bfd src/arch/x86/x86_traits.hh 7100059f7bfd Diff: http://reviews.gem5.org/r/1166/diff/ Testing ------- Boots Linux with atomic cpu. Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
