> On May 17, 2012, 11:25 p.m., Gabe Black wrote: > > src/arch/x86/isa/microops/regop.isa, line 442 > > <http://reviews.gem5.org/r/1166/diff/3/?file=26440#file26440line442> > > > > What are these constants? If this is splitting out the fields you > > mention in the commit message, that's already basically done. ccFlagBits > > means condition code flag bits. At the very least these constants should > > have names. Better yet, they should be derived from constants that already > > exist (ECFBit, EZFBit).
We need to figure out the individual register values after they have been updated by the genFlags() function. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1166/#review2703 ----------------------------------------------------------- On May 18, 2012, 11:55 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1166/ > ----------------------------------------------------------- > > (Updated May 18, 2012, 11:55 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9008:44471dbd9f5c > --------------------------- > X86: Split Condition Code register > This patch moves the ECF and EZF bits to the uccFlagBits and the CF and OF > bits to cfofFlag registers. Ultimately we will have the following registers > [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. > > > Diffs > ----- > > src/arch/x86/isa/microops/debug.isa 7100059f7bfd > src/arch/x86/isa/microops/fpop.isa 7100059f7bfd > src/arch/x86/isa/microops/mediaop.isa 7100059f7bfd > src/arch/x86/isa/microops/regop.isa 7100059f7bfd > src/arch/x86/isa/microops/seqop.isa 7100059f7bfd > src/arch/x86/isa/microops/specop.isa 7100059f7bfd > src/arch/x86/isa/operands.isa 7100059f7bfd > src/arch/x86/regs/misc.hh 7100059f7bfd > src/arch/x86/x86_traits.hh 7100059f7bfd > > Diff: http://reviews.gem5.org/r/1166/diff/ > > > Testing > ------- > > Boots Linux with atomic cpu. > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
