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(Updated May 19, 2012, 9:22 p.m.) Review request for Default. Description (updated) ------- Changeset 9010:b36a99151104 --------------------------- X86: Split Condition Code register This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Diffs (updated) ----- src/arch/x86/isa/microops/debug.isa d45a02bd5391 src/arch/x86/isa/microops/fpop.isa d45a02bd5391 src/arch/x86/isa/microops/mediaop.isa d45a02bd5391 src/arch/x86/isa/microops/regop.isa d45a02bd5391 src/arch/x86/isa/microops/seqop.isa d45a02bd5391 src/arch/x86/isa/microops/specop.isa d45a02bd5391 src/arch/x86/isa/operands.isa d45a02bd5391 src/arch/x86/regs/misc.hh d45a02bd5391 src/arch/x86/x86_traits.hh d45a02bd5391 Diff: http://reviews.gem5.org/r/1166/diff/ Testing ------- Boots Linux with atomic cpu. Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
