On 07/03/2013 01:01 AM, Ali Saidi wrote:
On 02.07.2013 17:45, Nilay Vaish wrote:
On Fri, 28 Jun 2013,
Andreas Sandberg wrote:
You're right about the uPC not being used in that case. However, still think
that it is a bad idea to allow a drained system to be in a microcode sequence.
My main concern is that
this will lead to subtle and hard to find bugs related to CPU switching
and it'll make the draining code harder to understand. Adding a
halt+eret would microop would solve the issue in a cleaner way in my
opinion.
Though I have not tested this patch with other ISAs, but I am guessing similar
issue can arise with them. Therefore, it would be better if we fix the cpu
model.
Does stopping in the middle prevent the virtualization code from working?
Yes. In order for virtualization to work, we need ensure that we never stop in
microcode. If the CPU is in the middle of a microcode sequence at a switch, we
won't know where to restart and restarting the current instruction is likely to
break (half of the side-effects might have executed and corrupted the state
needed to restart the instruction).
//Andreas
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
