On 11.07.2013 13:39, Nilay Vaish wrote:
> On Sun, 7 Jul 2013, Nilay Vaish wrote: > >> On Fri, 5 Jul 2013, Ali Saidi wrote: >> >>> Now lets say we're using the code that Andreas Sandberg committed ~6 months ago that lets you migrate execution between gem5 CPU models and a KVM virtual CPU. If you drain the system and stop in the middle of an instruction, there is no way the KVM virtual CPU is going to be able to pick up where you left off. >> Well, I would not call that a concrete example. And, in an x86 system, it seems there is a dependence between the boot cpu (cpu0) and others (cpu1). This means that if you are going to wait for cpu1 to get out of the Idle state while cpu0 has already drained, you will have a deadlock for sure. > > Are we done with the discussion here, or is there more to it? > > -- > Nilay > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev [1] I think that is a concrete example. We can't use the KVM switching code if "drained" in a CPU means you can be in the middle of a microcode sequence. Can you explain your situation more? I thought we determined there was no way into the Idle state? Thanks, Ali Links: ------ [1] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
