On 11.07.2013 18:16, Nilay Vaish wrote:
> On Thu, 11 Jul 2013, Ali Saidi wrote: > >> I think that is a concrete example. We can't use the KVM switching code if "drained" in a CPU means you can be in the middle of a microcode sequence. Can you explain your situation more? I thought we determined there was no way into the Idle state? > > You should probably read the entire thread. The link below points to mail > in which I explained the situation when a cpu can move to Idle in middle > of an instruction. > > http://www.mail-archive.com/[email protected]/msg09091.html [1] > > -- > Nilay > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev [2] Going back to my question, other than you starting the CPU in the Idle state, is there any way for it to get in there? If the only time this ever occurs is when one cpu hasn't actually booted yet, then I guess it will work. I still feel that Andreas' suggest about a halt and ret micro-op would be better. I think it will solve your immediate problem, since none of the cpus for my architecture of choice are going to stay in the idle state for after the first cycle of execution it doesn't matter to much to me, but it might be the source of subtle bugs with the non-interrupt ways to exit halt than Andreas mentioned. Ali Links: ------ [1] http://www.mail-archive.com/[email protected]/msg09091.html [2] http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
