> On June 27, 2013, 5:41 p.m., Andreas Hansson wrote: > > src/mem/SimpleDRAM.py, line 124 > > <http://reviews.gem5.org/r/1927/diff/2/?file=36306#file36306line124> > > > > I was not referring to the memory size of the system, rather I was > > thinking to use the parameter type Param.MemorySize. What do you think? > > Amin Farmahini wrote: > Sorry. I don't understand. Would you explain it a bit more? > Are you saying to use parameter type Param.MemorySize to calculate > rowbufferSize? > > Andreas Hansson wrote: > Not as much calculate as specify. Do you not think that makes more sense > than the implicit unit (bytes)?
Now I got it :). I do agree and will fix it. I think this is the last remaining issue. Please let me know if there is any thing else. If nothing's left, I'll fix this and will submit the new patch soon. - Amin ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1927/#review4478 ----------------------------------------------------------- On June 24, 2013, 6:01 a.m., Amin Farmahini wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1927/ > ----------------------------------------------------------- > > (Updated June 24, 2013, 6:01 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch gets rid of bytesPerCacheLine parameter and makes the DRAM > configuration separate from cache line size. > Instead of bytesPerCacheLine, I define a parameter for DRAM called > burst_length. The burst_length parameter shows the length of a DRAM device > burst in bits. > Also, I replace lines_per_rowbuffer with device_rowbuffer_size to improve > code portablity. > > Updates: > - a burst length in beats for each memory type. > - an interface width for each memory type. > - the memory controller model is extended to reason about "system" packets vs > "dram" packets and assemble the responses properly. It means that system > packets larger than a full burst are split into multiple dram packets. > > > Diffs > ----- > > src/mem/simple_dram.cc UNKNOWN > src/mem/simple_dram.hh UNKNOWN > src/mem/SimpleDRAM.py UNKNOWN > > Diff: http://reviews.gem5.org/r/1927/diff/ > > > Testing > ------- > > None > > > Thanks, > > Amin Farmahini > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
