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It looks much better with the comments. One potential concern is that we consider each memory range as a separate multi-channel DRAM controller. Hence, when we split 4 GB into 3 GB + 1 GB, we now create a (potentially multi-channel) controller per range. If the user says 4 channel DDR3, we now have 8 channels of DDR3. I don't know what is sensible to do here, but perhaps this solutions needs to be a bit more elaborate, and involve an AddrMapper one way or another? - Andreas Hansson On Jan. 20, 2014, 7:43 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2148/ > ----------------------------------------------------------- > > (Updated Jan. 20, 2014, 7:43 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10015:f67896fae8ec > --------------------------- > config: allow more than 3GB of memory for x86 simulations > This patch edits the configuration files so that x86 simulations can have > more than 3GB of memory. It also corrects a bug in the MemConfig.py script. > > > Diffs > ----- > > configs/common/FSConfig.py a362694dda2d > configs/common/MemConfig.py a362694dda2d > configs/example/fs.py a362694dda2d > > Diff: http://reviews.gem5.org/r/2148/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
