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(Updated Jan. 7, 2015, 10:07 p.m.) Review request for Default, Andrew Bardsley, Andreas Hansson, and Ali Saidi. Changes ------- Added details on testing done. Repository: gem5 Description ------- This change includes edits to Intel8254Timer to prevent counter events firing before startup to comply with SimObject initialization call sequence. Diffs ----- src/dev/alpha/tsunami_io.cc 9ac724889705 src/dev/intel_8254_timer.hh 9ac724889705 src/dev/intel_8254_timer.cc 9ac724889705 src/dev/mips/malta_io.cc 9ac724889705 src/dev/x86/i8254.hh 9ac724889705 src/dev/x86/i8254.cc 9ac724889705 Diff: http://reviews.gem5.org/r/2553/diff/ Testing (updated) ------- Run regression tests. After downloading all ARM tests, all tests are passing except: - EIO tests are skipped - SPARC tests are failing due to missing insttest and m5threads-test - X86 FS tests show changed stats. Thanks, Cagdas Dirik _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
