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src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/2691/#comment5249> Spelling mistake. - Nilay Vaish On March 14, 2015, 5:19 p.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2691/ > ----------------------------------------------------------- > > (Updated March 14, 2015, 5:19 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10745:9b84d1b570e3 > --------------------------- > mem: implement x86 locked accesses in timing-mode classic cache > > Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode, > use a combination of clearing permission bits and leaving > an MSHR in place to prevent accesses & snoops from touching > a locked block between the read and write parts of an locked > RMW sequence. > > > Diffs > ----- > > src/mem/cache/cache_impl.hh 655ff3f6352d7aa4021f8840b68698b277772806 > src/mem/packet.hh 655ff3f6352d7aa4021f8840b68698b277772806 > src/mem/packet.cc 655ff3f6352d7aa4021f8840b68698b277772806 > > Diff: http://reviews.gem5.org/r/2691/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
