> On April 8, 2015, 1:43 p.m., Stephan Diestelhorst wrote:
> > src/mem/cache/cache_impl.hh, line 1286
> > <http://reviews.gem5.org/r/2691/diff/1/?file=44226#file44226line1286>
> >
> > Why don't you break and drop the early_exit?
[Hmm, I had a comment here but reviewboard silently dropped it when I posted.]
Basically break doesn't work here because you still need to exit the code after
the if/else-if/else-if... sequence, but before the break. That is, the set of
lines starting with:
tgt_pkt->makeTimingResponse();
- Steve
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
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On May 6, 2015, 3:21 p.m., Steve Reinhardt wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2691/
> -----------------------------------------------------------
>
> (Updated May 6, 2015, 3:21 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> Changeset 10745:9b84d1b570e3
> ---------------------------
> mem: implement x86 locked accesses in timing-mode classic cache
>
> Add LockedRMW(Read|Write)(Req|Resp) commands. In timing mode,
> use a combination of clearing permission bits and leaving
> an MSHR in place to prevent accesses & snoops from touching
> a locked block between the read and write parts of an locked
> RMW sequence.
>
>
> Diffs
> -----
>
> src/mem/cache/cache_impl.hh fbdaa08aaa426b9f4660c366f934ccb670d954ec
> src/mem/cache/mshr.hh fbdaa08aaa426b9f4660c366f934ccb670d954ec
> src/mem/packet.hh fbdaa08aaa426b9f4660c366f934ccb670d954ec
> src/mem/packet.cc fbdaa08aaa426b9f4660c366f934ccb670d954ec
>
> Diff: http://reviews.gem5.org/r/2691/diff/
>
>
> Testing
> -------
>
>
> Thanks,
>
> Steve Reinhardt
>
>
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