> On May 15, 2015, 3:07 p.m., Nilay Vaish wrote:
> > src/mem/ruby/network/MessageBuffer.cc, line 320
> > <http://reviews.gem5.org/r/2805/diff/1/?file=45061#file45061line320>
> >
> >     Why is this change right?  Why can we move messages from one structure 
> > to another in zero time?

These structures are not meant to model hardware.  As the comment directly 
above this line states,  all stalled messages associated with this address are 
put back on the prio heap.  It is important that the reanalyzeList call ensures 
the consumer is scheduled for the current cycle so that the previously stalled 
messages will be observed before any younger messages that may arrive on the 
same cycle.


- Brad


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On May 11, 2015, 10:22 p.m., Tony Gutierrez wrote:
> 
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2805/
> -----------------------------------------------------------
> 
> (Updated May 11, 2015, 10:22 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> Changeset 10862:91c1912ec60e
> ---------------------------
> ruby: Fix for stallAndWait bug
> 
> It was previously possible for a stalled message to be reordered after an
> incomming message. This patch ensures that any stalled message stays in its
> original request order.
> 
> 
> Diffs
> -----
> 
>   src/mem/ruby/network/MessageBuffer.hh 
> fbdaa08aaa426b9f4660c366f934ccb670d954ec 
>   src/mem/ruby/network/MessageBuffer.cc 
> fbdaa08aaa426b9f4660c366f934ccb670d954ec 
>   src/mem/ruby/slicc_interface/AbstractController.hh 
> fbdaa08aaa426b9f4660c366f934ccb670d954ec 
>   src/mem/ruby/slicc_interface/AbstractController.cc 
> fbdaa08aaa426b9f4660c366f934ccb670d954ec 
> 
> Diff: http://reviews.gem5.org/r/2805/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Tony Gutierrez
> 
>

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