# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1236007007 18000
# Node ID 9a2e4b6c275a8513f040d4cb7604b2f8f25aeb68
# Parent bcb6c464587b1ef278165ff41442b226fed2a4a9
InOrder didnt have all it's params set to a default value, which is now
required for M5 objects; Also, a # of values need to be reset to 0 (or the
appropriate value) before we assume they are OK for use.
diff -r bcb6c464587b -r 9a2e4b6c275a src/cpu/inorder/InOrderCPU.py
--- a/src/cpu/inorder/InOrderCPU.py Mon Mar 02 10:16:46 2009 -0500
+++ b/src/cpu/inorder/InOrderCPU.py Mon Mar 02 10:16:47 2009 -0500
@@ -34,9 +34,8 @@ class InOrderCPU(BaseCPU):
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
activity = Param.Unsigned(0, "Initial count")
- numThreads = Param.Unsigned(1, "number of HW thread contexts")
- cachePorts = Param.Unsigned("Cache Ports")
+ cachePorts = Param.Unsigned(2, "Cache Ports")
stageWidth = Param.Unsigned(1, "Stage width")
fetchMemPort = Param.String("icache_port" , "Name of Memory Port to get
instructions from")
@@ -66,7 +65,7 @@ class InOrderCPU(BaseCPU):
functionTraceStart = Param.Tick(0, "Cycle to start function trace")
stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
- memBlockSize = Param.Unsigned("Memory Block Size")
+ memBlockSize = Param.Unsigned(64, "Memory Block Size")
multLatency = Param.Unsigned(1, "Latency for Multiply Operations")
multRepeatRate = Param.Unsigned(1, "Repeat Rate for Multiply Operations")
diff -r bcb6c464587b -r 9a2e4b6c275a src/cpu/inorder/comm.hh
--- a/src/cpu/inorder/comm.hh Mon Mar 02 10:16:46 2009 -0500
+++ b/src/cpu/inorder/comm.hh Mon Mar 02 10:16:47 2009 -0500
@@ -53,6 +53,15 @@ struct InterStageStruct {
uint64_t nextPC;
InstSeqNum squashedSeqNum;
bool includeSquashInst;
+
+ InterStageStruct()
+ {
+ size = 0;
+ mispredPC = nextPC = 0;
+ squash = branchMispredict = branchTaken = false;
+ squashedSeqNum = 0;
+ }
+
};
/** Turn This into a Class */
diff -r bcb6c464587b -r 9a2e4b6c275a src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc Mon Mar 02 10:16:46 2009 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.cc Mon Mar 02 10:16:47 2009 -0500
@@ -84,7 +84,10 @@ InOrderDynInst::InOrderDynInst(StaticIns
InOrderDynInst::InOrderDynInst()
: traceData(NULL), cpu(cpu)
-{ initVars(); }
+{
+ seqNum = 0;
+ initVars();
+}
int InOrderDynInst::instcount = 0;
diff -r bcb6c464587b -r 9a2e4b6c275a src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Mon Mar 02 10:16:46 2009 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Mon Mar 02 10:16:47 2009 -0500
@@ -38,34 +38,9 @@ using namespace ThePipeline;
using namespace ThePipeline;
PipelineStage::PipelineStage(Params *params, unsigned stage_num)
- : numThreads(ThePipeline::MaxThreads)
-{
- stageNum = stage_num;
- stageWidth = ThePipeline::StageWidth;
-
- _status = Inactive;
-
- prevStageValid = false;
- nextStageValid = false;
-
- // Init. structures
- for(int tid=0; tid < numThreads; tid++) {
- stageStatus[tid] = Idle;
-
- for (int stNum = 0; stNum < NumStages; stNum++) {
- stalls[tid].stage[stNum] = false;
- }
- stalls[tid].resources.clear();
-
- if (stageNum < BackEndStartStage)
- lastStallingStage[tid] = BackEndStartStage - 1;
- else
- lastStallingStage[tid] = NumStages - 1;
- }
-
- stageBufferMax = ThePipeline::interStageBuffSize[stage_num];
-}
-
+{
+ init(params, stage_num);
+}
void
PipelineStage::init(Params *params, unsigned stage_num)
@@ -189,7 +164,7 @@ PipelineStage::setNextStageQueue(TimeBuf
// Setup wire to write information to proper place in stage queue.
nextStage = nextStageQueue->getWire(0);
-
+ nextStage->size = 0;
nextStageValid = true;
}
@@ -682,6 +657,9 @@ PipelineStage::tick()
bool status_change = false;
+ if (nextStageValid)
+ nextStage->size = 0;
+
toNextStageIndex = 0;
sortInsts();
diff -r bcb6c464587b -r 9a2e4b6c275a src/cpu/inorder/resources/mult_div_unit.cc
--- a/src/cpu/inorder/resources/mult_div_unit.cc Mon Mar 02 10:16:46
2009 -0500
+++ b/src/cpu/inorder/resources/mult_div_unit.cc Mon Mar 02 10:16:47
2009 -0500
@@ -57,6 +57,8 @@ MultDivUnit::MultDivUnit(string res_name
div32RepeatRate = params->div32RepeatRate;
div32Latency = params->div32Latency;
+
+ lastMDUCycle = 0;
}
void
@@ -150,6 +152,9 @@ MultDivUnit::getSlot(DynInstPtr inst)
rval);
if (rval != -1) {
+ lastMDUCycle = curTick;
+ lastOpType = inst->opClass();
+ lastInstName = inst->staticInst->getName();
}
return rval;
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