# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1239339875 14400
# Node ID d4ff65e87a0bad86dd03c19fced4fdcd4ed68782
# Parent 0555121b5c5fb9fdfeb6f232421cf7a6c8d98b59
Edit AlphaISA to support the inorder model. Mostly alternate constructor
functions and also a few skeleton multithreaded support functions
diff -r 0555121b5c5f -r d4ff65e87a0b src/arch/SConscript
--- a/src/arch/SConscript Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/SConscript Fri Apr 10 01:04:35 2009 -0400
@@ -51,6 +51,7 @@ isa_switch_hdrs = Split('''
locked_mem.hh
microcode_rom.hh
mmaped_ipr.hh
+ mt.hh
process.hh
predecoder.hh
regfile.hh
diff -r 0555121b5c5f -r d4ff65e87a0b src/arch/alpha/floatregfile.hh
--- a/src/arch/alpha/floatregfile.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/floatregfile.hh Fri Apr 10 01:04:35 2009 -0400
@@ -42,6 +42,13 @@ class Checkpoint;
namespace AlphaISA {
+const int SingleWidth = 32;
+const int SingleBytes = SingleWidth / 4;
+const int DoubleWidth = 64;
+const int DoubleBytes = DoubleWidth / 4;
+const int QuadWidth = 128;
+const int QuadBytes = QuadWidth / 4;
+
class FloatRegFile
{
public:
@@ -54,6 +61,55 @@ class FloatRegFile
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+
+ FloatReg
+ readReg(int floatReg)
+ {
+ return d[floatReg];
+ }
+
+ FloatReg
+ readReg(int floatReg, int width)
+ {
+ return readReg(floatReg);
+ }
+
+ FloatRegBits
+ readRegBits(int floatReg)
+ {
+ return q[floatReg];
+ }
+
+ FloatRegBits
+ readRegBits(int floatReg, int width)
+ {
+ return readRegBits(floatReg);
+ }
+
+ void
+ setReg(int floatReg, const FloatReg &val)
+ {
+ d[floatReg] = val;
+ }
+
+ void
+ setReg(int floatReg, const FloatReg &val, int width)
+ {
+ setReg(floatReg, val);
+ }
+
+ void
+ setRegBits(int floatReg, const FloatRegBits &val)
+ {
+ q[floatReg] = val;
+ }
+
+ void
+ setRegBits(int floatReg, const FloatRegBits &val, int width)
+ {
+ setRegBits(floatReg, val);
+ }
+
};
} // namespace AlphaISA
diff -r 0555121b5c5f -r d4ff65e87a0b src/arch/alpha/miscregfile.cc
--- a/src/arch/alpha/miscregfile.cc Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/miscregfile.cc Fri Apr 10 01:04:35 2009 -0400
@@ -57,8 +57,15 @@ MiscRegFile::unserialize(Checkpoint *cp,
UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
}
+MiscRegFile::MiscRegFile(BaseCPU *_cpu)
+{
+ cpu = _cpu;
+ initializeIprTable();
+}
+
+
MiscReg
-MiscRegFile::readRegNoEffect(int misc_reg)
+MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -78,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_re
}
MiscReg
-MiscRegFile::readReg(int misc_reg, ThreadContext *tc)
+MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -97,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, Threa
}
void
-MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val)
+MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -123,7 +130,8 @@ MiscRegFile::setRegNoEffect(int misc_reg
}
void
-MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
+ unsigned tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff -r 0555121b5c5f -r d4ff65e87a0b src/arch/alpha/miscregfile.hh
--- a/src/arch/alpha/miscregfile.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/alpha/miscregfile.hh Fri Apr 10 01:04:35 2009 -0400
@@ -41,6 +41,7 @@
class Checkpoint;
class ThreadContext;
+class BaseCPU;
namespace AlphaISA {
@@ -68,6 +69,8 @@ class MiscRegFile
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
+ BaseCPU *cpu;
+
protected:
InternalProcReg readIpr(int idx, ThreadContext *tc);
void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
@@ -78,16 +81,18 @@ class MiscRegFile
initializeIprTable();
}
+ MiscRegFile(BaseCPU *cpu);
+
// These functions should be removed once the simplescalar cpu
// model has been replaced.
int getInstAsid();
int getDataAsid();
- MiscReg readRegNoEffect(int misc_reg);
- MiscReg readReg(int misc_reg, ThreadContext *tc);
+ MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
+ MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
- void setRegNoEffect(int misc_reg, const MiscReg &val);
- void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
+ void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned
tid = 0);
void
clear()
@@ -101,6 +106,16 @@ class MiscRegFile
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+
+ void reset(std::string core_name, unsigned num_threads,
+ unsigned num_vpes, BaseCPU *_cpu)
+ { }
+
+
+ void expandForMultithreading(unsigned num_threads, unsigned num_vpes)
+ { }
+
+
};
void copyIprs(ThreadContext *src, ThreadContext *dest);
diff -r 0555121b5c5f -r d4ff65e87a0b src/arch/mips/regfile/misc_regfile.hh
--- a/src/arch/mips/regfile/misc_regfile.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/arch/mips/regfile/misc_regfile.hh Fri Apr 10 01:04:35 2009 -0400
@@ -69,7 +69,7 @@ namespace MipsISA
public:
MiscRegFile();
- MiscRegFile(BaseCPU *cpu);
+ MiscRegFile(BaseCPU *_cpu);
void init();
diff -r 0555121b5c5f -r d4ff65e87a0b src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Wed Apr 08 22:21:30 2009 -0700
+++ b/src/cpu/inorder/cpu.cc Fri Apr 10 01:04:35 2009 -0400
@@ -820,6 +820,13 @@ InOrderCPU::removeThread(unsigned tid)
/** Broadcast to CPU resources*/
}
+PipelineStage*
+InOrderCPU::getPipeStage(int stage_num)
+{
+ return pipelineStage[stage_num];
+}
+
+
void
InOrderCPU::activateWhenReady(int tid)
{
diff -r 0555121b5c5f -r d4ff65e87a0b src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/cpu/inorder/cpu.hh Fri Apr 10 01:04:35 2009 -0400
@@ -308,6 +308,8 @@ class InOrderCPU : public BaseCPU
void deallocateThread(unsigned tid);
void deactivateThread(unsigned tid);
+ PipelineStage* getPipeStage(int stage_num);
+
int
contextId()
{
diff -r 0555121b5c5f -r d4ff65e87a0b src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Wed Apr 08 22:21:30 2009 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Fri Apr 10 01:04:35 2009 -0400
@@ -37,7 +37,10 @@
#include <list>
#include <string>
+#include "arch/isa_traits.hh"
#include "arch/faults.hh"
+#include "arch/types.hh"
+#include "arch/mt.hh"
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "cpu/inorder/inorder_trace.hh"
@@ -52,6 +55,9 @@
#include "cpu/inorder/pipeline_traits.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
+
+using namespace TheISA;
+
/**
* @file
@@ -829,6 +835,10 @@ class InOrderDynInst : public FastAlloc,
virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid
= -1);
+ /** Sets the number of consecutive store conditional failures. */
+ void setStCondFailures(unsigned sc_failures)
+ { thread->storeCondFailures = sc_failures; }
+
//////////////////////////////////////////////////////////////
//
// INSTRUCTION STATUS FLAGS (READ/SET)
diff -r 0555121b5c5f -r d4ff65e87a0b src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc Wed Apr 08 22:21:30 2009 -0700
+++ b/src/cpu/inorder/resources/cache_unit.cc Fri Apr 10 01:04:35 2009 -0400
@@ -32,7 +32,7 @@
#include <vector>
#include <list>
#include "arch/isa_traits.hh"
-#include "arch/mips/locked_mem.hh"
+#include "arch/locked_mem.hh"
#include "arch/utility.hh"
#include "cpu/inorder/resources/cache_unit.hh"
#include "cpu/inorder/pipeline_traits.hh"
diff -r 0555121b5c5f -r d4ff65e87a0b src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Wed Apr 08 22:21:30 2009 -0700
+++ b/src/cpu/inorder/resources/tlb_unit.cc Fri Apr 10 01:04:35 2009 -0400
@@ -33,6 +33,7 @@
#include <list>
#include "arch/isa_traits.hh"
#include "cpu/inorder/pipeline_traits.hh"
+#include "cpu/inorder/first_stage.hh"
#include "cpu/inorder/resources/tlb_unit.hh"
#include "cpu/inorder/cpu.hh"
@@ -82,7 +83,7 @@ TLBUnit::execute(int slot_idx)
// After this is working, change this to a reinterpret cast
// for performance considerations
TLBUnitRequest* tlb_req = dynamic_cast<TLBUnitRequest*>(reqMap[slot_idx]);
- assert(tlb_req);
+ assert(tlb_req != 0x0);
DynInstPtr inst = tlb_req->inst;
int tid, seq_num, stage_num;
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
