That's a legitimate problem. Would it work to pretend to do the access and save the request object for later? That should work with the timing versions of the ISAs as written from when they were changed to support delayed translation. initiateAcc no longer expects to find out about translation faults. I believe I changed your model to use translateAtomic() because it's basically identical to the old translate() and I didn't break anything that way, but it should really be translateTiming().
Gabe Korey Sewell wrote: > Hi Gabe, > the problem is that the inorder model needs to be able to do the TLB > translation separately from when it does the actual memory access. So > say cycle 1 could be translate, and cycle 2 could be access to the cache. > > The other CPU models do the TLB access and memory access all in one > function that takes the templated data type that is being written to > figure out the memory access size and flags. However, if I'm doing > this before I potentiall have the data, then I wouldnt know what this > information a priori. > > The size and flags are needed to create a request object which the TLB > needs to translate an address. > > I wish there was a cleaner way to do this, but this was the best > solution I came up with at the time. > > Any better ways you can think of? > > On Fri, Apr 10, 2009 at 2:17 AM, Gabe Black <[email protected] > <mailto:[email protected]>> wrote: > > Could you please explain what these new memAccFlags and memAccSize > functions are for and why they're needed? > > Korey Sewell wrote: > > # HG changeset patch > > # User Korey Sewell <[email protected] <mailto:[email protected]>> > > # Date 1239340019 14400 > > # Node ID dc1c89c97e02450a3b5302286904ab1e763f4300 > > # Parent 8542476836a75672fa06fe066e62b2b679319aea > > Expose memory access size and flags through instruction object > > > > diff -r 8542476836a7 -r dc1c89c97e02 src/arch/alpha/isa/mem.isa > > --- a/src/arch/alpha/isa/mem.isa Fri Apr 10 01:05:25 2009 -0400 > > +++ b/src/arch/alpha/isa/mem.isa Fri Apr 10 01:06:59 2009 -0400 > > @@ -65,6 +65,8 @@ output header {{ > > > > const StaticInstPtr &eaCompInst() const { return > eaCompPtr; } > > const StaticInstPtr &memAccInst() const { return > memAccPtr; } > > + > > + Request::Flags memAccFlags() { return memAccessFlags; } > > }; > > > > /** > > @@ -176,6 +178,8 @@ def template LoadStoreDeclare {{ > > %(InitiateAccDeclare)s > > > > %(CompleteAccDeclare)s > > + > > + %(MemAccSizeDeclare)s > > }; > > }}; > > > > @@ -190,6 +194,25 @@ def template CompleteAccDeclare {{ > > Trace::InstRecord *) const; > > }}; > > > > +def template MemAccSizeDeclare {{ > > + int memAccSize(%(CPU_exec_context)s *xc); > > +}}; > > + > > +def template MiscMemAccSize {{ > > + int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) > > + { > > + panic("Misc instruction does not support split access > method!"); > > + return 0; > > + } > > +}}; > > + > > +def template LoadStoreMemAccSize {{ > > + int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) > > + { > > + // Return the memory access size in bytes > > + return (%(mem_acc_size)d / 8); > > + } > > +}}; > > > > def template EACompConstructor {{ > > /** TODO: change op_class to AddrGenOp or something (requires > > @@ -617,6 +640,14 @@ def template MiscCompleteAcc {{ > > warn("Misc instruction does not support split access > method!"); > > > > return NoFault; > > + } > > +}}; > > + > > +def template MiscMemAccSize {{ > > + int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) > > + { > > + panic("Misc instruction does not support split access > method!"); > > + return 0; > > } > > }}; > > > > @@ -693,6 +724,11 @@ def LoadStoreBase(name, Name, ea_code, m > > initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') > > completeAccTemplate = eval(exec_template_base + 'CompleteAcc') > > > > + if (exec_template_base == 'Load' or exec_template_base == > 'Store'): > > + memAccSizeTemplate = eval('LoadStoreMemAccSize') > > + else: > > + memAccSizeTemplate = eval('MiscMemAccSize') > > + > > # (header_output, decoder_output, decode_block, exec_output) > > return (LoadStoreDeclare.subst(iop), > > EACompConstructor.subst(ea_iop) > > @@ -703,7 +739,8 @@ def LoadStoreBase(name, Name, ea_code, m > > + memAccExecTemplate.subst(memacc_iop) > > + fullExecTemplate.subst(iop) > > + initiateAccTemplate.subst(iop) > > - + completeAccTemplate.subst(iop)) > > + + completeAccTemplate.subst(iop) > > + + memAccSizeTemplate.subst(memacc_iop)) > > }}; > > > > def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, > > _______________________________________________ > > m5-dev mailing list > > [email protected] <mailto:[email protected]> > > http://m5sim.org/mailman/listinfo/m5-dev > > > > _______________________________________________ > m5-dev mailing list > [email protected] <mailto:[email protected]> > http://m5sim.org/mailman/listinfo/m5-dev > > > > > -- > ---------- > Korey L Sewell > Graduate Student - PhD Candidate > Computer Science & Engineering > University of Michigan > ------------------------------------------------------------------------ > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
