[m5-dev] [PATCH 03 of 10] Expose memory access size and flags through instruction object

[Korey Sewell]

# HG changeset patch
# User Korey Sewell <ksew...@umich.edu>
# Date 1239340019 14400
# Node ID dc1c89c97e02450a3b5302286904ab1e763f4300
# Parent  8542476836a75672fa06fe066e62b2b679319aea
Expose memory access size and flags through instruction object

diff -r 8542476836a7 -r dc1c89c97e02 src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa        Fri Apr 10 01:05:25 2009 -0400
+++ b/src/arch/alpha/isa/mem.isa        Fri Apr 10 01:06:59 2009 -0400
@@ -65,6 +65,8 @@ output header {{
 
         const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
         const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+        Request::Flags memAccFlags() { return memAccessFlags; }
     };
 
     /**
@@ -176,6 +178,8 @@ def template LoadStoreDeclare {{
         %(InitiateAccDeclare)s
 
         %(CompleteAccDeclare)s
+
+        %(MemAccSizeDeclare)s
     };
 }};
 
@@ -190,6 +194,25 @@ def template CompleteAccDeclare {{
                       Trace::InstRecord *) const;
 }};
 
+def template MemAccSizeDeclare {{
+    int memAccSize(%(CPU_exec_context)s *xc);
+}};
+
+def template MiscMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        panic("Misc instruction does not support split access method!");
+        return 0;
+    }
+}};
+
+def template LoadStoreMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        // Return the memory access size in bytes
+        return (%(mem_acc_size)d / 8);
+    }
+}};
 
 def template EACompConstructor {{
     /** TODO: change op_class to AddrGenOp or something (requires
@@ -617,6 +640,14 @@ def template MiscCompleteAcc {{
         warn("Misc instruction does not support split access method!");
 
         return NoFault;
+    }
+}};
+
+def template MiscMemAccSize {{
+    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+    {
+        panic("Misc instruction does not support split access method!");
+        return 0;
     }
 }};
 
@@ -693,6 +724,11 @@ def LoadStoreBase(name, Name, ea_code, m
     initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
     completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
 
+    if (exec_template_base == 'Load' or exec_template_base == 'Store'):
+      memAccSizeTemplate = eval('LoadStoreMemAccSize')
+    else:
+      memAccSizeTemplate = eval('MiscMemAccSize')
+
     # (header_output, decoder_output, decode_block, exec_output)
     return (LoadStoreDeclare.subst(iop),
             EACompConstructor.subst(ea_iop)
@@ -703,7 +739,8 @@ def LoadStoreBase(name, Name, ea_code, m
             + memAccExecTemplate.subst(memacc_iop)
             + fullExecTemplate.subst(iop)
             + initiateAccTemplate.subst(iop)
-            + completeAccTemplate.subst(iop))
+            + completeAccTemplate.subst(iop)
+            + memAccSizeTemplate.subst(memacc_iop))
 }};
 
 def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
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