# HG changeset patch
# User Korey Sewell <[email protected]>
# Date 1239339925 14400
# Node ID 8542476836a75672fa06fe066e62b2b679319aea
# Parent d4ff65e87a0bad86dd03c19fced4fdcd4ed68782
Separate the TLB from the CPU and allow it to live in the TLBUnit resource.
Give CPU accessor functions for access and also bind at construction time
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/cpu.cc Fri Apr 10 01:05:25 2009 -0400
@@ -178,14 +178,25 @@ InOrderCPU::InOrderCPU(Params *params)
// Bind the fetch & data ports from the resource pool.
fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
if (fetchPortIdx == 0) {
- warn("Unable to find port to fetch instructions from.\n");
+ fatal("Unable to find port to fetch instructions from.\n");
}
dataPortIdx = resPool->getPortIdx(params->dataMemPort);
if (dataPortIdx == 0) {
- warn("Unable to find port for data.\n");
- }
-
+ fatal("Unable to find port for data.\n");
+ }
+
+
+ // Hard-Code Bindings to ITB & DTB
+ itbIdx = resPool->getResIdx(name() + "." + "I-TLB");
+ if (itbIdx == 0) {
+ fatal("Unable to find ITB resource.\n");
+ }
+
+ dtbIdx = resPool->getResIdx(name() + "." + "D-TLB");
+ if (dtbIdx == 0) {
+ fatal("Unable to find DTB resource.\n");
+ }
for (int i = 0; i < numThreads; ++i) {
if (i < params->workload.size()) {
@@ -1258,3 +1269,18 @@ InOrderCPU::write(DynInstPtr inst)
Resource *mem_res = resPool->getResource(dataPortIdx);
return mem_res->doDataAccess(inst);
}
+
+TheISA::ITB*
+InOrderCPU::getITBPtr()
+{
+ TLBUnit *itb_res = dynamic_cast<TLBUnit*>(resPool->getResource(itbIdx));
+ return dynamic_cast<TheISA::ITB*>(itb_res->tlb());
+}
+
+
+TheISA::DTB*
+InOrderCPU::getDTBPtr()
+{
+ TLBUnit *dtb_res = dynamic_cast<TLBUnit*>(resPool->getResource(dtbIdx));
+ return dynamic_cast<TheISA::DTB*>(dtb_res->tlb());
+}
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/cpu.hh Fri Apr 10 01:05:25 2009 -0400
@@ -103,9 +103,6 @@ class InOrderCPU : public BaseCPU
Params *cpu_params;
- TheISA::TLB * itb;
- TheISA::TLB * dtb;
-
public:
enum Status {
Running,
@@ -236,10 +233,16 @@ class InOrderCPU : public BaseCPU
*/
unsigned fetchPortIdx;
+ /** Identifies the resource id that identifies a ITB */
+ unsigned itbIdx;
+
/** Identifies the resource id that identifies a data
* access unit.
*/
unsigned dataPortIdx;
+
+ /** Identifies the resource id that identifies a DTB */
+ unsigned dtbIdx;
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
@@ -261,6 +264,9 @@ class InOrderCPU : public BaseCPU
/** Communication structure that sits in between pipeline stages */
StageQueue *stageQueue[ThePipeline::NumStages-1];
+
+ TheISA::ITB *getITBPtr();
+ TheISA::DTB *getDTBPtr();
public:
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/resource_pool.cc Fri Apr 10 01:05:25 2009 -0400
@@ -143,6 +143,21 @@ ResourcePool::getPortIdx(const std::stri
return 0;
}
+unsigned
+ResourcePool::getResIdx(const std::string &res_name)
+{
+ DPRINTF(Resource, "Finding Resource Idx for %s.\n", res_name);
+
+ int num_resources = resources.size();
+
+ for (int idx = 0; idx < num_resources; idx++) {
+ if (resources[idx]->name() == res_name)
+ return idx;
+ }
+
+ return 0;
+}
+
ResReqPtr
ResourcePool::request(int res_idx, DynInstPtr inst)
{
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/resource_pool.hh Fri Apr 10 01:05:25 2009 -0400
@@ -131,8 +131,12 @@ class ResourcePool {
Port* getPort(const std::string &if_name, int idx);
/** Returns a specific port. */
- unsigned getPortIdx(const std::string &if_name);
+ unsigned getPortIdx(const std::string &port_name);
+ /** Returns a specific resource. */
+ unsigned getResIdx(const std::string &res_name);
+
+ /** Returns a pointer to a resource */
Resource* getResource(int res_idx) { return resources[res_idx]; }
/** Request usage of this resource. Returns -1 if not granted and
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.cc Fri Apr 10 01:05:25 2009 -0400
@@ -45,9 +45,24 @@ TLBUnit::TLBUnit(string res_name, int re
int res_latency, InOrderCPU *_cpu, ThePipeline::Params
*params)
: InstBuffer(res_name, res_id, res_width, res_latency, _cpu, params)
{
+ // Hard-Code Selection For Now
+ if (res_name == "I-TLB")
+ _tlb = params->itb;
+ else if (res_name == "D-TLB")
+ _tlb = params->dtb;
+ else
+ fatal("Unrecognized TLB name passed by user");
+
for (int i=0; i < MaxThreads; i++) {
tlbBlocked[i] = false;
}
+}
+
+TheISA::TLB*
+TLBUnit::tlb()
+{
+ return _tlb;
+
}
void
@@ -93,13 +108,16 @@ TLBUnit::execute(int slot_idx)
stage_num = tlb_req->getStageNum();
tlb_req->fault = NoFault;
+
+ assert(cpu->thread[tid]->getTC() != 0x0);
+ assert(cpu->pipelineStage[stage_num] != 0x0);
switch (tlb_req->cmd)
{
case FetchLookup:
{
tlb_req->fault =
- this->cpu->itb->translateAtomic(tlb_req->memReq,
+ _tlb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC(), false, true);
if (tlb_req->fault != NoFault) {
@@ -130,7 +148,7 @@ TLBUnit::execute(int slot_idx)
tid, seq_num, tlb_req->memReq->getVaddr());
tlb_req->fault =
- this->cpu->itb->translateAtomic(tlb_req->memReq,
+ _tlb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
if (tlb_req->fault != NoFault) {
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/resources/tlb_unit.hh
--- a/src/cpu/inorder/resources/tlb_unit.hh Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/resources/tlb_unit.hh Fri Apr 10 01:05:25 2009 -0400
@@ -67,14 +67,15 @@ class TLBUnit : public InstBuffer {
bool tlbBlocked[ThePipeline::MaxThreads];
+ TheISA::TLB* tlb();
+
protected:
/** List of instructions this resource is currently
* processing.
*/
std::list<DynInstPtr> instList;
- /** @todo: Add Resource Stats Here */
-
+ TheISA::TLB *_tlb;
};
class TLBUnitEvent : public ResourceEvent {
diff -r d4ff65e87a0b -r 8542476836a7 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Fri Apr 10 01:04:35 2009 -0400
+++ b/src/cpu/inorder/thread_context.hh Fri Apr 10 01:05:25 2009 -0400
@@ -57,7 +57,7 @@ class InOrderThreadContext : public Thre
public:
InOrderThreadContext() { }
- /** Pointer to the CPU. */
+ /** Pointer to the CPU. */
InOrderCPU *cpu;
/** Pointer to the thread state that this TC corrseponds to. */
@@ -65,10 +65,12 @@ class InOrderThreadContext : public Thre
/** Returns a pointer to the ITB. */
- TheISA::TLB *getITBPtr() { return cpu->itb; }
+ /** @TODO: PERF: Should we bind this to a pointer in constructor? */
+ TheISA::TLB *getITBPtr() { return cpu->getITBPtr(); }
/** Returns a pointer to the DTB. */
- TheISA::TLB *getDTBPtr() { return cpu->dtb; }
+ /** @TODO: PERF: Should we bind this to a pointer in constructor? */
+ TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
System *getSystemPtr() { return cpu->system; }
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