These patches enable Power ISA benchmarks to run on O3CPU through the following changes:
1) An alignment fault is added to the Power ISA. 2) The TLB translation mechanism is altered from atomic to timing. 3) Loads and stores are split in half if they cross a cache line boundary. The majority of the changes are in the LSQ Unit implementation where split loads and stores have to be handled correctly. -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336. _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
