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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/338/
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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan 
Binkert.


Summary
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O3: Fixes fetch deadlock when the interrupt master clears single before CPU 
handles it.
Then the cpu should restart fetch stage to fetch from the original execution
path.


Diffs
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  src/arch/arm/interrupts.hh 2b5fbdcbfb5d 
  src/cpu/o3/commit_impl.hh 2b5fbdcbfb5d 
  src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d 
  src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d 

Diff: http://reviews.m5sim.org/r/338/diff


Testing
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Thanks,

Ali

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